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OCP NIC 3.0 Design Specification
Version 1.1.01.0.91.00
Author: OCP Server Workgroup, OCP NIC subgroup
Style Definition: List Paragraph: Bulleted + Level: 1 +
Aligned at: 0.25" + Indent at: 0.5"
Open Compute Project OCP NIC 3.0
Rev Version 1.1.01.0.91.00
http://opencompute.org 2
Table of Contents
1 Overview ..........................................................................................................................................................................10
1.1 License ......................................................................................................................................................................... 10
1.2 Acknowledgements ..................................................................................................................................................... 11
1.3 References ................................................................................................................................................................... 12
1.3.1 Trademarks ........................................................................................................................................................ 13
1.4 Acronyms ..................................................................................................................................................................... 14
1.5 Conventions ................................................................................................................................................................. 15
1.6 Background .................................................................................................................................................................. 16
1.7 Overview ...................................................................................................................................................................... 18
1.7.1 Mechanical Form Factor Overview .................................................................................................................... 18
1.7.2 Electrical Overview ............................................................................................................................................ 20
1.7.2.1 Primary Connector ................................................................................................................................... 20
1.7.2.2 Secondary Connector ............................................................................................................................... 21
1.8 Non-NIC Use Cases ....................................................................................................................................................... 21
2 Mechanical Card Form Factor ...........................................................................................................................................23
2.1 Form Factor Options .................................................................................................................................................... 23
2.1.1 SFF Faceplate Configurations ............................................................................................................................. 25
2.1.2 LFF Faceplate Configurations ............................................................................................................................. 29
2.2 Line Side I/O Implementations .................................................................................................................................... 33
2.3 Top Level Assembly (SFF and LFF) ................................................................................................................................ 34
2.4 Faceplate Subassembly (SFF and LFF) .......................................................................................................................... 35
2.4.1 Faceplate Subassembly – Exploded View .......................................................................................................... 35
2.4.2 Faceplate Subassembly – Bill of Materials (BOM).............................................................................................. 35
2.4.3 SFF Generic I/O Faceplate .................................................................................................................................. 38
2.4.4 LFF Generic I/O Faceplate .................................................................................................................................. 39
2.4.5 Ejector Lever (SFF) ............................................................................................................................................. 40
2.4.6 Ejector Levers (LFF) ............................................................................................................................................ 41
2.4.7 Ejector Lock (SFF and LFF) .................................................................................................................................. 42
2.4.8 Clinch Nut (SFF and LFF) ..................................................................................................................................... 43
2.5 Card Keep Out Zones ................................................................................................................................................... 44
2.5.1 SFF Keep Out Zones ........................................................................................................................................... 44
2.5.2 LFF Keep Out Zones ........................................................................................................................................... 49
2.6 Baseboard Keep Out Zones .......................................................................................................................................... 54
2.7 Insulation Requirements .............................................................................................................................................. 55
2.7.1 SFF Insulator ...................................................................................................................................................... 55
2.7.2 LFF Insulator ....................................................................................................................................................... 57
2.8 Critical-to-Function (CTF) Dimensions (SFF and LFF) .................................................................................................... 60
2.8.1 CTF Tolerances ................................................................................................................................................... 60
2.8.2 SFF Pull Tab CTF Dimensions .............................................................................................................................. 60
2.8.3 SFF Ejector Latch CTF Dimensions ...................................................................................................................... 64
2.8.4 SFF Internal Lock CTF Dimensions ...................................................................................................................... 67
2.8.5 SFF Baseboard CTF Dimensions ......................................................................................................................... 70
2.8.6 LFF Ejector Latch CTF Dimensions ...................................................................................................................... 73
2.8.7 LFF Baseboard CTF Dimensions ......................................................................................................................... 76
2.9 Labeling Requirements ................................................................................................................................................ 79
2.9.1 General Guidelines for Label Contents .............................................................................................................. 79
2.9.2 MAC Address Labeling Requirements ................................................................................................................ 80
2.9.2.1 MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller ...................... 81
2.9.2.2 MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controllers ....................... 81
2.9.2.3 MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers ....................... 82
2.9.2.4 MAC Address Label Example 4 – Singe Port with Quad Host, Single Managed Controller ....................... 82
2.10 Mechanical CAD Package Examples ............................................................................................................................. 84
3 Electrical Interface Definition – Card Edge and Baseboard ................................................................................................85
3.1 Card Edge Gold Finger Requirements .......................................................................................................................... 85
3.1.1 Gold Finger Mating Sequence ............................................................................................................................ 87
3.2 Baseboard Connector Requirements ........................................................................................................................... 91
3.2.1 Right Angle Connector ....................................................................................................................................... 91
Open Compute Project OCP NIC 3.0
Rev Version 1.1.01.0.91.00
http://opencompute.org 3
3.2.2 Right Angle Offset .............................................................................................................................................. 92
3.2.3 Straddle Mount Connector ................................................................................................................................ 92
3.2.4 Straddle Mount Offset and PCB Thickness Options ........................................................................................... 94
3.2.5 LFF Connector Locations .................................................................................................................................... 95
3.3 Pin Definition ............................................................................................................................................................... 95
3.3.1 Primary Connector ............................................................................................................................................. 96
3.3.2 Secondary Connector ......................................................................................................................................... 98
3.4 Signal Descriptions ....................................................................................................................................................... 99
3.4.1 PCIe Interface Pins ............................................................................................................................................. 99
3.4.2 PCIe Present and Bifurcation Control Pins ....................................................................................................... 105
3.4.3 SMBus Interface Pins ....................................................................................................................................... 108
3.4.4 NC-SI over RBT Interface Pins .......................................................................................................................... 109
3.4.5 Scan Chain Pins ................................................................................................................................................ 117
3.4.6 Power Supply Pins ............................................................................................................................................ 126
3.4.7 USB 2.0 (A68/A69) – Primary Connector Only ................................................................................................. 131
3.4.8 UART (A68/A69) – Secondary Connector Only ................................................................................................ 133
3.4.9 RFU[1:4] Pins .................................................................................................................................................... 135
3.5 PCIe Bifurcation Mechanism ...................................................................................................................................... 136
3.5.1 PCIe OCP NIC 3.0 Card to Baseboard Bifurcation Configuration (PRSNTA#, PRSNTB[3:0]#) ............................ 136
3.5.2 PCIe Baseboard to OCP NIC 3.0 Card Bifurcation Configuration (BIF[2:0]#) .................................................... 136
3.5.3 PCIe Bifurcation Decoder ................................................................................................................................. 137
3.5.4 Bifurcation Detection Flow .............................................................................................................................. 139
3.5.5 PCIe Bifurcation Examples ............................................................................................................................... 140
3.5.5.1 Single Host (1 x16) Baseboard with a 1 x16 OCP NIC 3.0 Card (Single Controller) ................................. 140
3.5.5.2 Single Host (2 x8) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controllers) ...................................... 141
3.5.5.3 Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Single Controller) ...................................... 142
3.5.5.4 Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Quad Controllers) ..................................... 143
3.5.5.5 Single Host (1 x16, no Bifurcation) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controller) ............. 144
3.6 PCIe REFCLK and PERST# Mapping............................................................................................................................. 145
3.6.1 SFF PCIe REFCLK and PERST# Mapping ............................................................................................................ 146
3.6.2 LFF PCIe REFCLK and PERST# Mapping ............................................................................................................ 149
3.6.3 REFCLK and PERST# Mapping Expansion ......................................................................................................... 151
3.7 Port Numbering and LED Implementations ............................................................................................................... 152
3.7.1 OCP NIC 3.0 Port Naming and Port Numbering ............................................................................................... 152
3.7.2 OCP NIC 3.0 Card LED Configuration ................................................................................................................ 152
3.7.3 OCP NIC 3.0 Card LED Ordering ....................................................................................................................... 154
3.7.4 Baseboard LEDs Configuration over the Scan Chain ........................................................................................ 155
3.8 Power State Machine ................................................................................................................................................. 157
3.8.1 NIC Power Off .................................................................................................................................................. 160
3.8.2 ID Mode ........................................................................................................................................................... 160
3.8.3 Aux Power Mode ............................................................................................................................................. 161
3.8.4 Main Power Mode ........................................................................................................................................... 161
3.8.5 Programming Mode ......................................................................................................................................... 161
3.9 Power Supply Rail Requirements and Slot Power Envelopes ..................................................................................... 163
3.10 Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails ............................................................................. 164
3.11 Power Sequence Timing Requirements ..................................................................................................................... 166
3.12 Digital I/O Specifications ............................................................................................................................................ 176
4 Management and Pre-OS Requirements ......................................................................................................................... 177
4.1 Sideband Management Interface and Transport ....................................................................................................... 177
4.2 NC-SI Traffic ............................................................................................................................................................... 178
4.3 Management Controller (MC) MAC Address Provisioning ......................................................................................... 178
4.4 ASIC Die Temperature Reporting ............................................................................................................................... 180
4.5 Power Consumption Reporting .................................................................................................................................. 183
4.6 Pluggable Transceiver Module Status and Temperature Reporting .......................................................................... 184
4.7 Management and Pre-OS Firmware Inventory and Update ...................................................................................... 184
4.7.1 Secure Firmware .............................................................................................................................................. 184
4.7.2 Firmware Inventory ......................................................................................................................................... 185
4.7.3 Firmware Inventory and Update in Multi-Host Environments......................................................................... 185
Open Compute Project OCP NIC 3.0
Rev Version 1.1.01.0.91.00
http://opencompute.org 4
4.8 NC-SI Package Addressing and Hardware Arbitration Requirements ........................................................................ 186
4.8.1 NC-SI over RBT Package Addressing................................................................................................................. 186
4.8.2 Arbitration Ring Connections ........................................................................................................................... 186
4.9 SMBus 2.0 Addressing Requirements ........................................................................................................................ 186
4.9.1 SMBus Address Map ........................................................................................................................................ 187
4.10 FRU EEPROM .............................................................................................................................................................. 187
4.10.1 FRU EEPROM Addressing and Size ................................................................................................................... 187
4.10.2 FRU EEPROM Write Protection ........................................................................................................................ 189
4.10.3 FRU EEPROM Content Requirements .............................................................................................................. 189
4.10.4 FRU Template .................................................................................................................................................. 196
5 Routing Guidelines and Signal Integrity Considerations .................................................................................................. 197
5.1 NC-SI over RBT ........................................................................................................................................................... 197
5.1.1 SFF Baseboard Requirements .......................................................................................................................... 198
5.1.2 LFF Baseboard Requirements .......................................................................................................................... 199
5.1.3 SFF OCP NIC 3.0 Card Requirements ................................................................................................................ 199
5.1.4 LFF OCP NIC 3.0 Card Requirements ................................................................................................................ 200
5.2 SMBus 2.0 .................................................................................................................................................................. 200
5.3 PCIe ............................................................................................................................................................................ 201
5.3.1 Channel Requirements .................................................................................................................................... 201
5.3.1.1 REFCLK requirements ............................................................................................................................. 201
5.3.1.2 Add-in Card Electrical Budgets ............................................................................................................... 201
5.3.1.3 Baseboard Channel Budget .................................................................................................................... 202
5.3.1.4 SFF-TA-1002 Connector Channel Budget ............................................................................................... 202
5.3.1.5 Differential Impedance (Informative) .................................................................................................... 202
5.3.2 Test Fixtures ..................................................................................................................................................... 202
5.3.2.1 Compliance Load Board (CLB) ................................................................................................................ 203
5.3.2.2 Compliance Baseboard (CBB) ................................................................................................................. 204
5.3.3 Test Methodology ............................................................................................................................................ 204
5.3.3.1 Test Setup .............................................................................................................................................. 204
6 Thermal and Environmental ........................................................................................................................................... 206
6.1 Airflow Direction ........................................................................................................................................................ 206
6.1.1 Hot Aisle Cooling .............................................................................................................................................. 206
6.1.2 Cold Aisle Cooling ............................................................................................................................................ 207
6.2 Thermal Design Guidelines ........................................................................................................................................ 208
6.2.1 SFF Card ASIC Cooling – Hot Aisle .................................................................................................................... 208
6.2.2 LFF Card ASIC Cooling – Hot Aisle .................................................................................................................... 212
6.2.3 SFF Card ASIC Cooling – Cold Aisle ................................................................................................................... 214
6.2.4 LFF Card ASIC Cooling – Cold Aisle ................................................................................................................... 217
6.3 Thermal Simulation (CFD) Modeling .......................................................................................................................... 219
6.4 Thermal Test Fixture .................................................................................................................................................. 219
6.4.1 Test Fixture for SFF Card .................................................................................................................................. 220
6.4.2 Test Fixture for LFF Card .................................................................................................................................. 222
6.4.3 Test Fixture Airflow Direction .......................................................................................................................... 224
6.4.4 Thermal Test Fixture Candlestick Sensors........................................................................................................ 224
6.5 Card Sensor Requirements ........................................................................................................................................ 227
6.6 Card Cooling Tiers ...................................................................................................................................................... 227
6.7 Non-Operational Shock & Vibration Testing .............................................................................................................. 229
6.7.1 Shock & Vibe Test Fixture ................................................................................................................................ 229
6.7.2 Test Procedure ................................................................................................................................................. 230
6.8 Dye and Pull Test Method .......................................................................................................................................... 232
6.9 Gold Finger Plating Requirements ............................................................................................................................. 234
6.9.1 Host Side Gold Finger Plating Requirements ................................................................................................... 234
6.9.2 Line Side Gold Finger Durability Requirements ............................................................................................... 234
7 Regulatory...................................................................................................................................................................... 235
7.1 Required Compliance ................................................................................................................................................. 235
7.1.1 Required Environmental Compliance .............................................................................................................. 235
7.1.2 Required EMC Compliance .............................................................................................................................. 235
7.1.3 Required Product Safety Compliance .............................................................................................................. 236
Open Compute Project OCP NIC 3.0
Rev Version 1.1.01.0.91.00
http://opencompute.org 5
7.1.4 Required Immunity (ESD) Compliance ............................................................................................................. 236
7.2 Recommended Compliance ....................................................................................................................................... 237
7.2.1 Recommended Environmental Compliance..................................................................................................... 237
7.2.2 Recommended EMC Compliance ..................................................................................................................... 237
8 Revision History ............................................................................................................................................................. 238
8.1 Document Revision History ........................................................................................................................................ 238
8.2 FRU Content Revision History .................................................................................................................................... 246
List of Figures
Figure 1: Representative SFF OCP NIC 3.0 Card with Dual QSFP Ports ........................................................................................... 16
Figure 2: Representative LFF OCP NIC 3.0 Card with Dual QSFP Ports and on-board DRAM .......................................................... 17
Figure 3: SFF and LFF Block Diagrams (not to scale) ....................................................................................................................... 18
Figure 4: Primary Connector (4C+) and Secondary Connector (4C) (LFF) OCP NIC 3.0 Cards ......................................................... 23
Figure 5: Primary Connector (4C+) Only (LFF) OCP NIC 3.0 Cards ................................................................................................... 24
Figure 6: Primary Connector (4C+) with 4C and 2C (SFF) OCP NIC 3.0 Cards .................................................................................. 24
Figure 7: SFF NIC Configuration Views ............................................................................................................................................ 26
Figure 8: SFF NIC Line Side 3D Views .............................................................................................................................................. 27
Figure 9: SFF NIC Chassis Mounted 3D Views ................................................................................................................................. 28
Figure 10: LFF NIC Configuration Views .......................................................................................................................................... 30
Figure 11: LFF NIC Line Side 3D Views ............................................................................................................................................ 31
Figure 12: LFF NIC Chassis Mounted 3D Views ............................................................................................................................... 32
Figure 13: PBA Exploded Views (SFF and LFF) ................................................................................................................................. 34
Figure 14: Faceplate Assembly Exploded Views (SFF and LFF) ........................................................................................................ 35
Figure 15: SFF Generic I/O Faceplate with Pulltab Version (2D View) ............................................................................................ 38
Figure 16: SFF Generic I/O Faceplate – Ejector Version (2D View) ................................................................................................. 38
Figure 17: SFF Generic I/O Faceplate – Internal Lock Version (2D View) ........................................................................................ 39
Figure 18: LFF Generic I/O Faceplate – Ejector Version (2D View) ................................................................................................. 39
Figure 19: SFF I/O Faceplate – Ejector Lever (2D View) .................................................................................................................. 40
Figure 20: LFF I/O Faceplate – Ejector Lever (2D View) .................................................................................................................. 41
Figure 21: Ejector Lock .................................................................................................................................................................... 42
Figure 22: Clinch Nut Option A ....................................................................................................................................................... 43
Figure 23: Clinch Nut Option B........................................................................................................................................................ 43
Figure 24: SFF Keep Out Zone – Top View ...................................................................................................................................... 44
Figure 25: SFF Keep Out Zone – Top View – Detail A ...................................................................................................................... 47
Figure 26: SFF Keep Out Zone – Bottom View ................................................................................................................................ 47
Figure 27: SFF Keep Out Zone – Side View ...................................................................................................................................... 48
Figure 28: SFF Keep Out Zone – Side View – Detail D ..................................................................................................................... 48
Figure 29: LFF Keep Out Zone – Top View ...................................................................................................................................... 49
Figure 30: LFF Keep Out Zone – Top View – Detail A ...................................................................................................................... 52
Figure 31: LFF Keep Out Zone – Bottom View ................................................................................................................................ 53
Figure 32: LFF Keep Out Zone – Side View ...................................................................................................................................... 53
Figure 33: LFF Keep Out Zone – Side View – Detail D ..................................................................................................................... 54
Figure 34: SFF Bottom Side Insulator (3D View) ............................................................................................................................. 55
Figure 35: SFF Bottom Side Insulator (Top and Side View) ............................................................................................................. 56
Figure 36: SFF Bottom Side Insulator (alternate) (Top and Side View) ........................................................................................... 57
Figure 37: LFF Bottom Side Insulator (3D View) ............................................................................................................................. 57
Figure 38: LFF Bottom Side Insulator (Top and Side View) ............................................................................................................. 58
Figure 39: LFF Bottom Side Insulator (alternate) (Top and Side View) ........................................................................................... 59
Figure 40: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View) ................................................................................... 60
Figure 41: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View) ................................................................................. 62
Figure 42: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View) .................................................................................. 62
Figure 43: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View) ..................................................................................... 64
Figure 44: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View) .................................................................................. 66
Figure 45: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View) .................................................................................... 67
Figure 46: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View) ........................................................................... 67
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