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Document Number: MD00047

Revision 3.10

July 5, 2005

MIPS Technologies, Inc.

1225 Charleston Road

Mountain View, CA 94043-1353

EJTAG Speciﬁcation

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EJTAG Specification, Revision 3.10

Template: B1.14, Built with tags: 2B

EJTAG Specification, Revision 3.10 i

Table of Contents

Chapter 1 The EJTAG System ..............................................................................................................................................1

1.1 Introduction to EJTAG ............................................................................................................................................1

1.2 Historical Perspective .............................................................................................................................................1

1.3 EJTAG Capabilities ................................................................................................................................................4

1.3.1 Debug Exception and Debug Mode ..............................................................................................................4

1.3.2 Off-board EJTAG Memory ...........................................................................................................................5

1.3.3 Debug Breakpoint Instruction .......................................................................................................................5

1.3.4 Hardware Breakpoints ..................................................................................................................................5

1.3.5 Single-Step Execution ...................................................................................................................................5

1.4 EJTAG Components and Options ...........................................................................................................................6

1.4.1 EJTAG Processor Core Extensions ..............................................................................................................6

1.4.2 EJTAG Test Access Port ..............................................................................................................................7

1.4.3 Debug Control Register ................................................................................................................................7

1.4.4 Hardware Breakpoint Unit ............................................................................................................................7

1.5 EJTAG-Specific Coprocessor 0 Registers ..............................................................................................................7

1.6 Memory-Mapped EJTAG Registers .......................................................................................................................8

1.6.1 Debug Control Register ................................................................................................................................8

1.6.2 Instruction Hardware Breakpoint Registers ..................................................................................................8

1.6.3 Data Hardware Breakpoint Registers ............................................................................................................9

1.7 Memory-Mapped EJTAG Memory Segment .........................................................................................................9

1.8 EJTAG Test Access Port Registers .......................................................................................................................10

1.9 The Implications of Multiprocessing and Multithreading for EJTAG .................................................................10

1.10 Related Documents .............................................................................................................................................11

1.11 Notations and Conventions .................................................................................................................................11

1.11.1 Compliance ...............................................................................................................................................11

1.11.2 UNPREDICTABLE and UNDEFINED Operations ................................................................................12

1.11.3 Register Field Notations ...........................................................................................................................13

1.11.4 Value Notations ........................................................................................................................................13

1.11.5 Address Notations .....................................................................................................................................13

Chapter 2 Debug Control Register ......................................................................................................................................15

Chapter 3 Hardware Breakpoints ........................................................................................................................................19

3.1 Introduction ...........................................................................................................................................................19

3.1.1 Instruction Breakpoint Features ..................................................................................................................20

3.1.2 Data Breakpoint Features ............................................................................................................................20

3.2 Overview of Instruction and Data Breakpoint Registers ......................................................................................20

3.2.1 Overview of Instruction Breakpoint Registers ...........................................................................................21

3.2.2 Overview of Data Breakpoint Registers .....................................................................................................21

3.3 Conditions for Matching Breakpoints ...................................................................................................................22

3.3.1 Conditions for Matching Instruction Breakpoints ......................................................................................22

3.3.2 Conditions for Matching Data Breakpoints ................................................................................................24

3.4 Debug Exceptions from Breakpoints ....................................................................................................................28

3.4.1 Debug Exception Caused by Instruction Breakpoint ..................................................................................28

3.4.2 Debug Exception by Data Breakpoint ........................................................................................................29

3.5 Breakpoints Used as Triggerpoints .......................................................................................................................31

3.6 Instruction Breakpoint Registers ...........................................................................................................................31

3.6.1 Instruction Breakpoint Status (IBS) Register .............................................................................................32

3.6.2 Instruction Breakpoint Address n (IBAn) Register ....................................................................................33

3.6.3 Instruction Breakpoint Address Mask n (IBMn) Register ..........................................................................34

3.6.4 Instruction Breakpoint ASID n (IBASIDn) Register ..................................................................................34

ii EJTAG Specification, Revision 3.10

3.6.5 Instruction Breakpoint Control n (IBCn) Register ......................................................................................35

3.7 Data Breakpoint Registers ....................................................................................................................................37

3.7.1 Data Breakpoint Status (DBS) Register ......................................................................................................37

3.7.2 Data Breakpoint Address n (DBAn) Register .............................................................................................39

3.7.3 Data Breakpoint Address Mask n (DBMn) Register ..................................................................................39

3.7.4 Data Breakpoint ASID n (DBASIDn) Register ..........................................................................................40

3.7.5 Data Breakpoint Control n (DBCn) Register ..............................................................................................41

3.7.6 Data Breakpoint Value n (DBVn) Register ................................................................................................43

3.8 Recommendations for Implementing Hardware Breakpoints ...............................................................................44

3.8.1 Number of Instruction Breakpoints Without Single Stepping ....................................................................44

3.8.2 Data Breakpoints with Data Value Compares ............................................................................................44

3.8.3 Data Breakpoint Compare on Invalid Data .................................................................................................44

3.8.4 Precise / Imprecise Debug Exceptions on Data Breakpoints with Data Value Compares .........................45

3.9 Breakpoint Examples ............................................................................................................................................45

3.9.1 Instruction Breakpoint Examples ................................................................................................................45

3.9.2 Data Breakpoint ..........................................................................................................................................46

Chapter 4 PC Sampling .......................................................................................................................................................49

4.1 Introduction ...........................................................................................................................................................49

4.2 Overview of the PC Sampling Feature .................................................................................................................49

4.2.1 PC Sampling in Wait State .........................................................................................................................50

4.2.2 PC Sampling a MT Processor .....................................................................................................................50

Chapter 5 EJTAG Processor Core Extensions ....................................................................................................................51

5.1 Overview ...............................................................................................................................................................51

5.2 Debug Mode Execution ........................................................................................................................................51

5.2.1 Debug Mode Instruction Set .......................................................................................................................52

5.2.2 Debug Mode Address Space .......................................................................................................................52

5.2.3 Debug Mode Handling of Processor Resources .........................................................................................56

5.2.4 CP0 and dseg Segment Hazards .................................................................................................................58

5.3 Debug Exceptions .................................................................................................................................................60

5.3.1 Debug Exception Priorities .........................................................................................................................60

5.3.2 Debug Exception Vector Location ..............................................................................................................61

5.3.3 General Debug Exception Processing .........................................................................................................61

5.3.4 Debug Breakpoint Exception ......................................................................................................................62

5.3.5 Debug Instruction Break Exception ............................................................................................................63

5.3.6 Debug Data Break Load/Store Exception ...................................................................................................63

5.3.7 Debug Data Break Load/Store Imprecise Exception ..................................................................................63

5.3.8 Debug Single Step Exception .....................................................................................................................64

5.3.9 Debug Interrupt Exception ..........................................................................................................................67

5.4 Debug Mode Exceptions .......................................................................................................................................68

5.4.1 Exceptions Taken in Debug Mode ..............................................................................................................68

5.4.2 Exceptions on Imprecise Errors ..................................................................................................................69

5.4.3 Debug Mode Exception Processing ............................................................................................................69

5.5 Interrupts and NMIs ..............................................................................................................................................70

5.5.1 Interrupts .....................................................................................................................................................70

5.5.2 NMIs ...........................................................................................................................................................71

5.6 Reset and Soft Reset of Processor .........................................................................................................................71

5.6.1 EJTAGBOOT Feature ................................................................................................................................71

5.6.2 Reset from Probe .........................................................................................................................................71

5.6.3 Processor Reset by Probe through Test Access Port ..................................................................................71

5.6.4 Reset Occurred Indication through Test Access Port .................................................................................72

5.6.5 Soft Reset Enable ........................................................................................................................................72

5.6.6 Reset of Other Debug Features ...................................................................................................................72

5.7 EJTAG Instructions ...............................................................................................................................................72

5.7.1 DERET Instruction .....................................................................................................................................74

EJTAG Specification, Revision 3.10 iii

5.8 EJTAG Coprocessor 0 Registers ...........................................................................................................................75

5.8.1 Debug Register (CP0 Register 23, Select 0) ...............................................................................................75

5.8.2 Debug Exception Program Counter Register (CP0 Register 24, Select 0) .................................................83

5.8.3 Debug Exception Save Register (CP0 Register 31, Select 0) .....................................................................83

Chapter 6 EJTAG Test Access Port ....................................................................................................................................85

6.1 TAP Overview ......................................................................................................................................................85

6.2 TAP Signals ..........................................................................................................................................................86

6.2.1 Test Clock Input (TCK) ..............................................................................................................................86

6.2.2 Test Mode Select Input (TMS) ...................................................................................................................86

6.2.3 Test Data Input (TDI) .................................................................................................................................87

6.2.4 Test Data Output (TDO) .............................................................................................................................87

6.2.5 Test Reset Input (TRST*) ...........................................................................................................................87

6.3 TAP Controller ......................................................................................................................................................87

6.3.1 Test-Logic-Reset State ................................................................................................................................88

6.3.2 Capture-IR State ..........................................................................................................................................88

6.3.3 Shift-IR State ..............................................................................................................................................88

6.3.4 Update-IR State ...........................................................................................................................................89

6.3.5 Capture-DR State ........................................................................................................................................89

6.3.6 Shift-DR State .............................................................................................................................................89

6.3.7 Update-DR State .........................................................................................................................................89

6.4 Instruction Register and Special Instructions ........................................................................................................89

6.4.1 ALL Instruction ..........................................................................................................................................91

6.4.2 EJTAGBOOT and NORMALBOOT Instructions ......................................................................................91

6.4.3 FASTDATA Instruction .............................................................................................................................91

6.5 TAP Data Registers ...............................................................................................................................................92

6.5.1 Device Identification (ID) Register (TAP Instruction IDCODE) ...............................................................93

6.5.2 Implementation Register (TAP Instruction IMPCODE) ............................................................................94

6.5.3 Data Register (TAP Instruction DATA, ALL, or FASTDATA) ................................................................96

6.5.4 Address Register (TAP Instruction ADDRESS or ALL) ...........................................................................99

6.5.5 EJTAG Control Register (ECR) (TAP Instruction CONTROL or ALL) ...................................................99

6.5.6 Fastdata Register (TAP Instruction FASTDATA) ...................................................................................105

6.5.7 PCsample Register (PCSAMPLE Instruction) .........................................................................................106

6.5.8 Bypass Register (TAP Instruction BYPASS, (EJTAG/NORMAL)BOOT, or Unused) ..........................107

6.6 Examples of Use .................................................................................................................................................107

6.6.1 TAP Operation ..........................................................................................................................................108

6.6.2 ManufID Value .........................................................................................................................................108

6.6.3 Rocc Bit Usage .........................................................................................................................................108

6.6.4 EJTAG Memory Access Through Processor Access ................................................................................109

Chapter 7 On-Chip Interfaces ...........................................................................................................................................113

7.1 Connecting Unused EJTAG Test Access Port and Debug Interrupt Signals ......................................................113

7.2 Optional TRST* Pin ............................................................................................................................................113

7.3 Input Buffers with Pull-Up/Down and Output Drivers for Chip Pins ................................................................113

7.4 Connecting Multi-Core Test Access Port (TAP) Controllers .............................................................................114

Chapter 8 Off-Chip and Probe Interfaces ..........................................................................................................................115

8.1 Logical Signals ....................................................................................................................................................115

8.1.1 Test Access Port Signals ...........................................................................................................................116

8.1.2 Debug Interrupt Signal ..............................................................................................................................117

8.1.3 System Reset Signal ..................................................................................................................................117

8.1.4 Voltage Sense for I/O Signal ....................................................................................................................117

8.2 AC Timing Characteristics ..................................................................................................................................118

8.2.1 Test Access Port Timing ...........................................................................................................................118

8.2.2 Debug Interrupt Timing ............................................................................................................................119

8.2.3 System Reset Timing ................................................................................................................................120