JEDEC Standard No. 21C, Release 29 DDR4 SDRAM Registered DIMM Design Specification
Page 4.20.28-2 Revision 1.50
Table of Contents
1 Product Description .............................................................................................. 5
2 Environmental Requirements .............................................................................. 6
3 Connector Pinout and Signal Description .......................................................... 7
4 Power Details....................................................................................................... 12
4.1 DIMM Voltage Requirements.................................................................................. 12
4.2 VDDSPD .................................................................................................................. 12
4.3 Recommended Power Sequence........................................................................... 12
4.4 Feed Through Voltage (VFT).................................................................................. 14
4.5 12 V Power............................................................................................................... 14
5 Component Details.............................................................................................. 15
5.1 Component Types and Placement ........................................................................ 18
5.2 Decoupling Guidelines ........................................................................................... 18
6 DIMM Design Details ........................................................................................... 19
6.1 Signal Groups.......................................................................................................... 19
6.2 General Net Structure Routing Rules.................................................................... 19
6.2.1 Clock, Control, and Address/Command Groups ........................................................... 21
6.2.2 PreRegister ADD/CMD and CTRL ................................................................................21
6.2.3 PreRegister CK .............................................................................................................21
6.2.4 PostRegister ADD/CMD ................................................................................................22
6.2.5 PostRegister CTRL Group ............................................................................................ 23
6.2.6 DQ Group ......................................................................................................................23
6.3 Modified Rules for RDIMM Designs at 2666 Mbps and Higher and 16 Gb......... 24
6.4 Plane Referencing................................................................................................... 25
6.5 Address Mirroring................................................................................................... 25
6.6 DQ Mapping to Support CRC................................................................................. 27
6.7 DIMM Routing Space Constraints ......................................................................... 31
6.8 DIMM Physical Requirements................................................................................ 32
6.8.1 Via Size .........................................................................................................................32
6.8.2 Component Pad Sizes and Geometry........................................................................... 32
6.8.3 SDRAM Package Size ..................................................................................................32
6.8.4 Clock Termination .........................................................................................................32
6.8.5 DQ Resistor...................................................................................................................33
6.9 RDIMM Configuration ............................................................................................. 33
6.9.1 Control Wiring................................................................................................................33
6.9.2 AVDD Filter Circuit, Placement and Wiring ...................................................................35
6.9.3 ZQ Calibration Wiring .................................................................................................... 35
6.9.4 ALERT_n Circuit Wiring ................................................................................................35
6.9.5 TEN Pin Wiring ..............................................................................................................36
6.10 SPD-TSE Selection, Wiring and Placement.......................................................... 36
7 Serial Presence Detect (Pending Separate Ballot) ........................................... 37
7.1 Serial Presence Detect Definition.......................................................................... 37
8 Product Label ...................................................................................................... 40
9 JEDEC Process ................................................................................................... 45
Downloaded by James Zhang (pat12155@gmail.com) on Feb 11, 2020, 7:48 pm PST
Wistron
我的内容管理
收起
我的收益 登录查看自己的收益
我的积分
登录查看自己的积分
我的C币
登录后查看C币余额
我的收藏 
我的下载 
下载帮助 
评论0