富士通单片机（MB90F549G）_富士通各个引脚

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DS07-13703-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

MC-16LX MB90540/545 Series

MB90F543/F549/V540

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DESCRIPTION

The MB90540/545 series with FULL-CAN*

and FLASH ROM is specially designed for automotive and industrial ap-

plications. Its main features are two on board CAN Interfaces (one for MB90V545 series), which conform to V2.0

Part A and Part B, supporting very flexible message buffer

scheme and so offering more functions than a normal

full CAN approach. The instruction set by F

MC-16LX CPU core inherits an AT architecture of the F

MC*

family with

additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division in-

structions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing

long word data.The MB90540/545 series has peripheral resources of 8/10-bit A/D converters, UART(SCI), extended

I/O serial interfaces, 8/16-bit timer, I/O timer (input capture(ICU), output compare (OCU)).

*1:Controller Area Network (CAN) - License of Robert Bosch GmbH.

*2:F

MC stands for FUJITSU Flexible Microcontroller.

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FEATURES

•Clock

Embedded PLL clock multiplication circuit

Operating clock (PLL clock) can be selected from: divided-by-2 of oscillation or one to four times the oscillation

Minimum instruction execution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,

CC of 5.0V)

Subsystem Clock: 32 kHz

(Continued)

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PACKAGE

100-pin Plastic QFP

(FPT-100P-M06)

查询MB90F546G供应商

MB90540/545 Series

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PRODUCT LINEUP

The following table provides a quick outlook of the MB90540/545 Series

(Continued)

Features MB90F543 MB90F549 MB90V540

Classification Flash ROM product Evaluation product

ROM size

128 Kbytes

Boot Block

256 Kbytes

Boot Block

None

ROM size 6 K 8 K

CPU functions

The number of instructions: 351

Instruction bit length: 8 bits, 16 bits

Instruction length: 1 byte to 7 bytes

Data bit length: 1bit, 8 bits, 16 bits

Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)

Interrupt processing time: 1.5 µs (at machine clock frequency of 16 MHz, minimum value)

UART 0

Clock synchronized transmission (500 K / 1M / 2 Mbps)

Clock asynchronized transmission (4808 / 5208 / 9615 / 10417 / 19230 / 38460 / 62500

/500000 bps at machine clock frequency of 16 MHz)

Transmission can be performed by bi-directional serial transmission or by master/slave

connection.

UART 1 (SCI)

Clock synchronized transmission (62.5 K/ 12 K/ 250 K/ 500 K/ 1 Mbps)

Clock asynchronized transmission (1202/ 2404/ 4808/ 9615/ 31250 bps)

Transmission can be performed by bi-directional serial

Transmission or by master / slave connection.

8/10-bit A/D converter

Conversion precision: 8/10-bit can be selectively used.

Number of inputs: 8

One-shot conversion mode (converts selected channel once only)

Scan conversion mode (converts two or mode successive channels and can program up

to 8 channels)

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

8/16-bit PPG timers

Number of channels: 8/16 bit × 4 channels

PPG operation of 8-bit or 16 bit

A pulse wave of given intervals and given duty ratios can be output.

Pulse interval: fsys, fsys/2

, fsys/2

, 128 µs

(at oscillation of 4 MHz, fsys = machine clock frequency of 16 MHz, fosc = oscillation clock

frequency)

16-bit Reload timer

Number of channels:2

Operation clock frequency: fsys/2

, fsys/2

(fsys = System clock frequency)

Supports External Event Count function

16-bit

I/O

timer

16-bit

Output com-

pares

Number of channels: 4

Pin input factor: A match signal of compare register

Input cap-

tures

Number of channels: 8

Rewriting a register value upon a pin input (rising, falling, or both edges)

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