JEDEC Standard No. 79-3E
Contents
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1 Scope..........................................................................................................................................1
2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
2.1 DDR3 SDRAM x4 Ballout using MO-207........................................................................3
2.2 DDR3 SDRAM x8 Ballout using MO-207........................................................................4
2.3 DDR3 SDRAM x16 Ballout using MO-207......................................................................5
2.4 Stacked / dual-die DDR3 SDRAM x4 Ballout using MO-207..........................................6
2.5 Stacked / dual-die DDR3 SDRAM x8 Ballout using MO-207..........................................7
2.6 Stacked / dual-die DDR3 SDRAM x16 Ballout using MO-207........................................8
2.7 Quad-stacked / Quad-die DDR3 SDRAM x4 Ballout using MO-207...............................9
2.8 Quad-stacked / Quad-die DDR3 SDRAM x8 Ballout using MO-207.............................10
2.9 Quad-stacked / Quad-die DDR3 SDRAM x16 Ballout using MO-207...........................11
2.10 Pinout Description..........................................................................................................13
2.11 DDR3 SDRAM Addressing...........................................................................................15
2.11.1 512Mb ....................................................................................................................15
2.11.2 1Gb..........................................................................................................................15
2.11.3 2Gb .........................................................................................................................15
2.11.4 4Gb .........................................................................................................................15
2.11.5 8Gb .........................................................................................................................16
3 Functional Description.............................................................................................................17
3.1 Simplified State Diagram.................................................................................................17
3.2 Basic Functionality ..........................................................................................................18
3.3 RESET and Initialization Procedure ................................................................................19
3.3.1 Power-up Initialization Sequence .............................................................................19
3.3.2 Reset Initialization with Stable Power......................................................................21
3.4 Register Definition...........................................................................................................22
3.4.1 Programming the Mode Registers ............................................................................22
3.4.2 Mode Register MR0..................................................................................................23
3.4.3 Mode Register MR1..................................................................................................27
3.4.4 Mode Register MR2..................................................................................................30
3.4.5 Mode Register MR3..................................................................................................32
4 DDR3 SDRAM Command Description and Operation...........................................................33
4.1 Command Truth Table .....................................................................................................33
4.2 CKE Truth Table..............................................................................................................35
4.3 No OPeration (NOP) Command ......................................................................................36
4.4 Deselect Command ..........................................................................................................36
4.5 DLL-off Mode..................................................................................................................37
4.6 DLL on/off switching procedure......................................................................................38
4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38
4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39
4.7 Input clock frequency change ..........................................................................................40
4.8 Write Leveling .................................................................................................................42
4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43
4.8.2 Procedure Description...............................................................................................43
4.8.3 Write Leveling Mode Exit ........................................................................................45
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更新于2023-03-03
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