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音频解码芯片PCM510X 中文数据手册,来源于网络资源,具有PLL和32位音频输出2.1VRMS,音频立体声DAC,工作电压3.3V
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PCM510xA
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLAS859
PCM5100A
,
PCM5101A
,
PCM5102A
PCM5100A-Q1
,
PCM5101A-Q1
,
PCM5102A-Q1
ZHCSA60C –MAY 2012–REVISED MAY 2015
PCM510xA具具有有 PLL 和和 32 位位、、384kHz PCM 接接口口的的 2.1 V
RMS
、、
112/106/100dB 音音频频立立体体声声 DAC
1
1 特特性性
1
• 超低带外噪声
• 具有 BCK 基准的高性能集成音频锁相环 (PLL),可
在内部生成 SCK
• 直接线路电平 2.1 V
RMS
输出
• 无需隔直电容
• 线路电平输出支持低至 1kΩ 的负载
• 智能静音系统;软斜升或斜降搭配模拟静音,实现
120dB 静音信噪比 (SNR)
• 接收 16、24 和 32 位音频数据
• PCM 数据样式:I
2
S,左对齐
• 当 LRCK 和 BCK 被置为无效时,自动进入省电模
式
• 1.8V 或3.3V 故障安全低压 CMOS (LVCMOS) 数
字输入
• 采用硬件引脚的简易配置
• 单电源供电:14
– 3.3V 模拟电源、1.8V 或3.3V 数字电源
• 符合 AEC-Q100 标准
2 应应用用
• A/V 接收器、DVD、BD 播放器
• 汽车信息娱乐系统和远程信息处理
• HDTV 接收器
• 汽车售后加装放大器
3 说说明明
PCM510xA 器件属于单片 CMOS 集成电路系列,由立
体声数模转换器 (DAC) 和采用薄型小外形尺寸
(TSSOP) 封装的附加支持电路组成。PCM510xA 器件
使用 TI 最新一代高级分段 DAC 架构产品,可实现出
色的动态性能并提升针对时钟抖动的耐受度。
凭借 DirectPath™电荷泵技术,PCM510xA 器件提供
2.1 V
RMS
中央接地输出(设计人员无需在输出上连接
隔直电容)以及传统意义上与单电源线路驱动器相关的
外部静音电路。
集成线路驱动器的每个引脚支持低至 1kΩ 的负载,从
而在性能上超过其他所有基于电荷泵的线路驱动器。
器件上集成的 PLL 免除了对于系统时钟(通常称为主
时钟)的需要,从而实现一个 3 线制 I
2
C 连接并减少
了系统电磁干扰 (EMI)。
智能时钟误差与 PowerSense 欠压保护采用双层系
统,能够消除喀嗒和噼啪声。
相比许多传统的开关电容 DAC 架构,PCM510xA 系
列能够将带外噪声控制在 20dB 的较低水平,从而减少
下游放大器/ADC 中的 EMI 和混叠(在 100kHz(OBN
典型值)到 3MHz 之间测得)。
表表 1. 器器件件信信息息
(1)
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
PCM5102A
TSSOP (20) 5.50mm x 4.40mmPCM5101A
PCM5100A
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
4 简简化化系系统统图图
中的器件编号“PCM510x”至“PCM510xA”

2
PCM5100A
,
PCM5101A
,
PCM5102A
PCM5100A-Q1
,
PCM5101A-Q1
,
PCM5102A-Q1
ZHCSA60C –MAY 2012–REVISED MAY 2015
www.ti.com.cn
版权 © 2012–2015, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 简简化化系系统统图图............................................................... 1
5 修修订订历历史史记记录录 ........................................................... 2
6 Device Comparison ............................................... 4
7 Pin Configuration and Functions......................... 5
8 Specifications......................................................... 6
8.1 Absolute Maximum Ratings ...................................... 6
8.2 ESD Ratings ............................................................ 6
8.3 Recommended Operating Conditions....................... 6
8.4 Thermal Information.................................................. 6
8.5 Electrical Characteristics........................................... 7
8.6 Timing Requirements.............................................. 11
8.7 Timing Requirements, XSMT.................................. 11
8.8 Typical Characteristics............................................ 12
9 Detailed Description............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 25
10 Applications and Implementation...................... 26
10.1 Application Information.......................................... 26
11 Power Supply Recommendations ..................... 28
11.1 Power Supply Distribution and Requirements ...... 28
11.2 Recommended Powerdown Sequence................. 28
11.3 External Power Sense Undervoltage Protection
Mode ........................................................................ 30
11.4 Power-On Reset Function..................................... 32
11.5 PCM510xA Power Modes..................................... 33
12 Layout................................................................... 34
12.1 Layout Guidelines ................................................. 34
13 器器件件和和文文档档支支持持 ..................................................... 35
13.1 相关链接................................................................ 35
13.2 社区资源................................................................ 35
13.3 商标 ....................................................................... 35
13.4 静电放电警告......................................................... 35
14 机机械械、、封封装装和和可可订订购购信信息息....................................... 35
14.1 机械数据................................................................ 35
5 修修订订历历史史记记录录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision B (January 2015) to Revision C Page
• 已更改
简化系统图
.................................................................................................................................................................. 1
• Changed typical performance table to reflect part differences accurately ............................................................................ 4
• Changed "Storage temperatures, T
stg
" to "Operating junction temperature range at –40°C to 130°C" ................................. 6
• Changed "Storage temperature (Q1 devices) –40°C to 125°C" to "Storage temperatures, T
stg
–65°C to 150°C" ................ 6
• Changed the stereo line output load resistance MIN value in the Recommended Operating Conditions from "2 kΩ"
to "1 kΩ".................................................................................................................................................................................. 6
• Changed the operating junction temperature range in the Recommended Operating Conditions from "MIN = –25°C
MAX = 85°C" to "MIN = –40°C MAX = 130°C"....................................................................................................................... 6
• Added "Q1 Automotive grade devices... " and " Consumer grade (non-Q1) devices..." to the condition statement in
the Electrical Characteristics .................................................................................................................................................. 7
• Added "Q1 Automotive grade devices... " and " Consumer grade (non-Q1) devices..." to the condition statement in
the Typical Characteristics graphs section........................................................................................................................... 12
• 已更改 "MCK" to "SCK" at the PLL Clock in the Functional Block Diagram ........................................................................ 14
• Added label "Mute Circuit" and ground symbols to pins DEMP and FMT in Figure 33 ...................................................... 26
Changes from Revision A (September 2012) to Revision B Page
• 已添加 ESD
额定值
表,
详细 说明
部分,
应用和实施
部分,
电源相关建议
部分,
器件和文档支持
部分以及
机械、封装
和可订购信息
.......................................................................................................................................................................... 1
• 已添加 1.8V DVDD 电源项 ..................................................................................................................................................... 1
• 已更改
特性
列表。 .................................................................................................................................................................. 1
• Changed "Operating temperature range " to "Operating junction temperature range" .......................................................... 6
• Deleted redundant PLL specification in the Recommended Operating Conditions .............................................................. 6
• 已删除 "Intelligent clock error..." and "...for pop-free performance." .................................................................................... 14
• Clarified clock generation explanation.................................................................................................................................. 24

3
PCM5100A
,
PCM5101A
,
PCM5102A
PCM5100A-Q1
,
PCM5101A-Q1
,
PCM5102A-Q1
www.ti.com.cn
ZHCSA60C –MAY 2012–REVISED MAY 2015
Copyright © 2012–2015, Texas Instruments Incorporated
• Clarified external SCK discussion. ....................................................................................................................................... 25
• Deleted "The PCM510xA disables the internal PLL when an external SCK is supplied." ................................................... 25
Changes from Original (May 2012) to Revision A Page
• 已更改 前两页的编排 .............................................................................................................................................................. 1
• Changed "VOUT = –1 dB" to "THD+N at –1 dBFS" in in the Dymamic Performance section of the Electrical
Characteristics........................................................................................................................................................................ 8
• Changed reference to correct footnote................................................................................................................................. 10
• Changed t
SCKH
and t
SCKL
values to 9ns................................................................................................................................. 11
• Removed 48kHz sample rate with PLL-generated clock...................................................................................................... 25

4
PCM5100A
,
PCM5101A
,
PCM5102A
PCM5100A-Q1
,
PCM5101A-Q1
,
PCM5102A-Q1
ZHCSA60C –MAY 2012–REVISED MAY 2015
www.ti.com.cn
Copyright © 2012–2015, Texas Instruments Incorporated
6 Device Comparison
Differences Between PCM510xA Devices
PART NUMBER DYNAMIC RANGE SNR THD
PCM5102A 112dB 112dB –93 dB
PCM5101A 106 dB 106 dB –92 dB
PCM5100A 100 dB 100 dB –90 dB
Typical Performance (3.3 V Power Supply)
PARAMETER PCM5102 / PCM5101 / PCM5100
SNR 112 / 106 / 100 dB
Dynamic range 112 /106 / 100 dB
THD+N at –1 dBFS –93/ –92 / –90 dB
Full-scale single-ended output 2.1 V
RMS
(GND center)
Normal 8× oversampling digital filter latency 20t
S
Low latency 8× oversampling digital filter latency 3.5t
S
Sampling frequency 8 kHz to 384 kHz
System clock multiples (f
SCK
): 64, 128, 192, 256, 384,
512, 768, 1024, 1152, 1536, 2048, 3072
Up to 50 MHz

5
PCM5100A
,
PCM5101A
,
PCM5102A
PCM5100A-Q1
,
PCM5101A-Q1
,
PCM5102A-Q1
www.ti.com.cn
ZHCSA60C –MAY 2012–REVISED MAY 2015
版权 © 2012–2015, Texas Instruments Incorporated
(1) Failsafe LVCMOS Schmitt trigger input
7 Pin Configuration and Functions
PW 20-Pin Package
(Top View)
Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
AGND 9 — Analog ground
AVDD 8 P Analog power supply, 3.3 V
BCK 13 I Audio data bit clock input
(1)
CAPM 4 O Charge pump flying capacitor terminal for negative rail
CAPP 2 O Charge pump flying capacitor terminal for positive rail
CPGND 3 — Charge pump ground
CPVDD 1 P Charge pump power supply, 3.3 V
DEMP 10 I De-emphasis control for 44.1-kHz sampling rate
(1)
: Off (Low) / On (High)
DGND 19 — Digital ground
DIN 14 I Audio data input
(1)
DVDD 20 P Digital power supply, 1.8 V or 3.3 V
FLT 11 I Filter select : Normal latency (Low) / Low latency (High)
FMT 16 I Audio format selection : I
2
S (Low) / Left-justified (High)
LDOO 18 P Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal
LRCK 15 I Audio data word clock input
(1)
OUTL 6 O Analog output from DAC left channel
OUTR 7 O Analog output from DAC right channel
SCK 12 I System clock input
(1)
VNEG 5 O Negative charge pump rail terminal for decoupling, –3.3 V
XSMT 17 I Soft mute control
(1)
: Soft mute (Low) / soft un-mute (High)
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