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V0.3 Page 1 of 83 2018/12
ST7262
1200CH System-On-Chip Driver for 800RGBx480
TFT LCD
Datasheet
Sitronix reserves the right to change the contents in this
document without prior notice, please contact Sitronix to
obtain the latest version of datasheet before placing your
order. No responsibility is assumed by Sitronix for any
infringement of patent or other rights of third parties which
may result from its use.
2018 Sitronix Technology Corporation. All rights reserved.
Version 0.3
2018/12
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
ST7262
V0.3 Page 2 of 83 2018/11
LIST OF CONTENT
1. GENERAL DESCRIPTION ........................................................................ 5
2. FEATURES ............................................................................................... 6
3. PAD ARRANGEMENT .............................................................................. 7
3.2 Bump Dimension ...................................................................................................... 8
3.3 Alignment Mark Dimension ...................................................................................... 8
4. PAD CENTER COORDINATES ................................................................ 9
5. BLOCK DIAGRAM .................................................................................. 40
6. PIN DESCRIPTION ................................................................................. 41
6.1 Pin Function ........................................................................................................... 41
6.2 Hardware Pin Option Mapping Software Register Option ...................................... 45
7. COMMUNICATION INTERFACE ............................................................ 46
7.1 3-wire Serial Interface ............................................................................................ 46
7.2 I
2
C Interface ........................................................................................................... 47
7.2.1 Bit Transfer ............................................................................................................................... 47
7.2.2 START and STOP Conditions.................................................................................................. 47
7.2.3 System Configuration ............................................................................................................... 48
7.2.4 Acknowledgment ...................................................................................................................... 48
7.2.5 I
2
C Interface Protocol ............................................................................................................... 49
7.3 RGB Interface ........................................................................................................ 50
7.3.1 SYNC Mode ............................................................................................................................. 50
7.3.2 SYNC-DE Mode ....................................................................................................................... 51
7.3.3 DE Mode .................................................................................................................................. 52
7.3.4 Parallel 24-bit RGB Input Timing Table ................................................................................... 52
7.4 LVDS Interface....................................................................................................... 53
7.4.1 4 Lane VESA Data Format Color Bit Map ................................................................................ 53
7.4.2 4 Lane JEIDA Data Format Color Bit Map ............................................................................... 53
8. REGISTER LIST ...................................................................................... 54
8.1 Register Summary ................................................................................................. 54
8.2 Command Table1 Register Description ................................................................. 57
8.2.1 GRB、DISP CONTROL (10h) ................................................................................................. 57
8.2.2 CONTRAST (11h) .................................................................................................................... 57
8.2.3 SUB_CONTRAST_R (12h) ...................................................................................................... 57
8.2.4 SUB_CONTRAST_B (13h) ...................................................................................................... 58
8.2.5 BRIGHTNESS (14h) ................................................................................................................ 58
8.2.6 SUB-BRIGHTNESS_R (15h) ................................................................................................... 58
8.2.7 SUB-BRIGHTNESS_B (16h) ................................................................................................... 59
8.2.8 H_BLANKING (17h) ................................................................................................................. 59
8.2.9 V_BLANKING (18h) ................................................................................................................. 59
ST7262
V0.3 Page 3 of 83 2018/12
8.2.10 DISPLAY MODE SETTING (19h) .......................................................................................... 60
8.2.11 RGB INTERFACE POLARITY SETTING (1Bh)..................................................................... 60
8.3 Command Table2 Register Description ................................................................. 61
8.3.1 GVDD SETTING (40h) ............................................................................................................. 61
8.3.2 GVCL SETTING (41h) ............................................................................................................. 62
8.3.3 VGH, VGL SETTING (45h) ...................................................................................................... 63
8.3.4 SOURCE EQUALIZE TIME SETTING (46h) ........................................................................... 63
8.3.5 SOURCE OP-AMP POWER SETTING (47h) .......................................................................... 63
8.4 Gamma Table Register Description ....................................................................... 64
8.4.1 GAMMA SETTING (20h~29h, 30h~39h) ................................................................................. 64
8.5 OTP Table Register Description ............................................................................ 66
8.5.1 ID1 SETTING (01h) .................................................................................................................. 66
8.5.2 ID2 SETTING (02h) .................................................................................................................. 66
8.5.3 ID3 SETTING (03h) .................................................................................................................. 66
8.5.4 I2C ID CODE SETTING (04h).................................................................................................. 66
8.5.5 VCOM OFFSET SETTING (05h) ............................................................................................. 67
8.5.6 OTP FUNCTION CONTROL (60h) .......................................................................................... 67
8.5.7 OTP ACKNOWLEDGEMENT CONTROL (65h) ...................................................................... 68
8.5.8 VCOM OFFSET OTP PROGRAM TIMES (66h) ...................................................................... 68
8.5.9 COMMAND 2 PROGRAM TIMES (67h) .................................................................................. 68
8.5.10 GAMMA OTP PROGRAM TIMES (68h) ................................................................................ 68
8.5.11 ID1 OTP PROGRAM TIMES (69h) ........................................................................................ 69
8.5.12 ID2 OTP PROGRAM TIMES (6Ah) ........................................................................................ 69
8.5.13 ID3 OTP PROGRAM TIMES (6Bh) ........................................................................................ 69
8.5.14 I
2
C ID OTP PROGRAM TIMES (6Ch) .................................................................................... 69
9. ELECTRICAL SPECIFICATIONS ........................................................... 70
9.1 Absolute Maximum Ratings ................................................................................... 70
9.2 DC Characteristics ................................................................................................. 71
9.2.1 Recommended Operating Range ............................................................................................ 71
9.2.2 DC Characteristics for Digital Circuit ........................................................................................ 71
9.2.3 DC Characteristics for Analog Circuit ...................................................................................... 71
9.2.4 DC Characteristics for LVDS Receiver Circuit ......................................................................... 72
9.3 AC Characteristics ................................................................................................. 73
9.3.1 System Operation AC Characteristics ..................................................................................... 73
9.3.2 System Bus Timing for I
2
C Interface ........................................................................................ 74
9.3.3 System Bus Timing for 3-Wire SPI Interface ........................................................................... 75
9.3.4 System Bus Timing for RGB Interface ..................................................................................... 76
9.3.5 System Bus Timing for LVDS Interface ................................................................................... 78
10. APPLICATION CIRCUIT ....................................................................... 79
10.1 External Component of Power Circuit .................................................................. 79
ST7262
V0.3 Page 4 of 83 2018/12
11. POWER ON/OFF SEQUENCE .............................................................. 80
11.1 Power On Sequence ............................................................................................ 80
11.2 Power Off Sequence ............................................................................................ 80
12. RECOMMENDED PANEL ROUTING RESISTANCE ............................ 81
13. COLOR FILTER ARRANGEMENT ....................................................... 82
14. REVISION HISTORY ............................................................................. 83
ST7262
V0.3 Page 5 of 83 2018/12
1. GENERAL DESCRIPTION
IC offers all-in-one chip solution of 800RGBx480 for color dual gate TFT-LCD panel. The driver IC output
ports consists of 1200 source channels and 20 gate control channels for panel application. This chip
incorporated with digital timing generator, source and gate driver, power supply circuit and embedded 3-wire
SPI and I
2
C interfaces for function setting. The display data bits sent from MCU via LVDS interface or RGB
interface directly related to the pixels of LCD panel. The source output supports 256 gray scale with real 8-bit
DAC to get a small output deviation for high color resolution. The power supply circuit incorporated with step-
up circuit, regulators and operational amplifiers to generate power supply voltages to drive TFT LCD.
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