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JetsonXavierNXDatasheet_v1.6.pdf
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NVIDIA® Jetson Xavier™ NX brings AI supercomputer performance to the edge in a compact system-on-module (SOM) that’s smaller than a credit card. Jetson Xavier NX is built around a low-power version of the NVIDIA Xavier SoC, combining the NVIDIA Volta™ GPU architecture with 64-bit operating capabilit
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JETSON | Xavier NX | DATA SHEET | DS-10184-001 | SUBJECT TO CHANGE | COPYRIGHT © 2014 – 2020 NVIDIA CORPORATION. ALL RIGHTS RESERVED. 1
DATA SHEET
NVIDIA Jetson Xavier NX System-on-Module
Volta GPU + Carmel CPU + 8 GB LPDDR4x + 16 GB eMMC 5.1
AI Performance
Up to 21 TOPS (INT8)
Volta GPU
384 NVIDIA
®
CUDA
®
cores | 48 Tensor cores | End-to-end lossless
compression | Tile Caching | OpenGL
®
4.6 | OpenGL ES 3.2 |
Vulkan™ 1.1
◊
| CUDA 10 | Maximum Operating Frequency: 1100
MHz
Carmel CPU
ARMv8.2 (64-bit) heterogeneous multi-processing (HMP) CPU
architecture | 3x dual-core CPU clusters (six NVIDIA Carmel
processor cores) connected by a high-performance system
coherency interconnect fabric | L3 Cache: 4 MB (shared across all
clusters)
NVIDIA Carmel (Dual-Core) Processor: L1 Cache: 128 KB L1
instruction cache (I-cache) per core; 64 KB L1 data cache (D-
cache) per core | L2 Unified Cache: 2 MB per cluster | Maximum
Operating Frequency: 1900 MHz
Audio
Dedicated programmable audio processor | ARM Cortex A9 with
NEON | PDM in/out | Industry-standard High Definition Audio (HDA)
controller provides a multi-channel audio path to the HDMI
®
interface
Memory
8 GB 128-bit LPDDR4x DRAM | Secure External Memory Access
Using TrustZone
®
Technology | System MMU | Maximum Operating
Frequency: 1600 MHz
Storage
16 GB eMMC 5.1 Flash Storage | Bus Width: 8-bit | Maximum Bus
Frequency: 200 MHz (HS400)
Networking
10/100/1000 Gigabit Ethernet | Media Access Controller (MAC)
Imaging
14 lanes (3 x4 or 6 x2) MIPI CSI-2 | D-PHY 1.2 (2.5 Gb/s per pair,
total up to 30 Gbps)
Display Controller
Two multi-mode (eDP/DP/HDMI) Serial Output Resources (SOR)
eDP 1.4a | DP 1.4 | HDMI 2.0a/b
Maximum Resolution (eDP/DP/HDMI): (up to) 3840x2160 at 60 Hz
(up to 36 bpp)
Multi-Stream HD Video and JPEG
Video Decode:
• Standards supported: H.265 (HEVC), H.264, VP9, VP8,
MPEG-4, MPEG-2, VC-1
o 2x690 MP/sec (HEVC)
o 2x 4K @ 60 (HEVC)
o 4x 4K @ 30 (HEVC)
o 12x 1080p @ 60 (HEVC)
o 32x 1080p @ 30 (HEVC)
o 16x 1080p @ 30 (H.264)
Video Encode:
• Standards supported: H.265 (HEVC), H.264, VP9
o 2x464 MP/sec (HEVC)
o 2x 4K @ 30 (HEVC)
o 6x 1080p @ 60 (HEVC)
o 14x 1080p @ 30 (HEVC)
Peripheral Interfaces
xHCI host controller with integrated PHY (up to) 1x USB 3.1, 3x
USB 2.0 | PCIe 1x1 (GEN3) + 1x4 (GEN4) | SD/MMC controller
(supporting eMMC 5.1, SD 4.0, SDHOST 4.0 and SDIO 3.0) | 3x
UART | 2x SPI | 4x I
2
C | 1x CAN | 2x I
2
S | GPIOs
Mechanical
Module Size: 69.6 mm x 45 mm | 260 pin SO-DIMM Connector
Operating Requirements
Temperature Range (T
J
)*: -25°C – 90°C | Supported Power
Modes: 10W – 15W | Power Input: 5V
Note: Refer to the Software Features section of the latest L4T Development Guide for a list of supported features; all features may not be
available.
◊
Product is based on a published Khronos Specification and is expected to pass the Khronos Conformance Process. Current conformance status
can be found at www.khronos.org/conformance.
* See the Jetson Xavier NX Thermal Design Guide for details
Jetson Xavier NX System-on-Module
Volta GPU + Carmel CPU + 8GB LPDDR4x + 16GB eMMC 5.1
JETSON | Xavier NX | DATA SHEET | DS-10184-001 | SUBJECT TO CHANGE | COPYRIGHT © 2014 – 2020 NVIDIA CORPORATION. ALL RIGHTS RESERVED. 2
Revision History
Version
Date
Description
V1.0
November 6, 2019
Initial release.
V1.1
February 1, 2020
Updated:
• PCIE0_XXX pins from Ctrl #0 to Ctrl #5 under PCIe Pin description in Table 9: PCIe
Pin Descriptions
• PCIE1_XXX pins from Ctrl #1 to Ctrl #4 under PCIe Pin description in Table 9: PCIe
Pin Descriptions
• Pulse Width Modulator (PWM) to reflect four outputs instead of eight outputs
• SHUTDOWN_REQ* and SYS_RESET* pull up information in Table 21: Power and
System Control Pins
• Table 29: Absolute Maximum Ratings to include the Mounting Force parameter.
• Mechanical Drawing
V1.2
February 24, 2020
Added:
• Tolerance information for Mechanical Drawing
V1.3
April 21, 2020
Added:
• PMIC_BBAT to reflect RTC accuracy
• SoC height for the Mechanical Drawing
• Table 30: Jetson NX Reliability Report table
• Gen4 information to PCI Express (PCIe) section
V1.4
June 25, 2020
Added:
• Programmable Vision Accelerator (PVA) section to Functional Overview
Updated:
• Table 6: Video Decoder Standards table
V1.5
July 06, 2020
Added:
• Overcurrent Throttling section to Power and System Management
V1.6
October 23, 2020
Updated:
• SHUTDOWN_REQ* pin changed from Input to Output
• Document number of data sheet
Added:
• SPI Slave Timing Parameters and Diagram
Jetson Xavier NX System-on-Module
Volta GPU + Carmel CPU + 8GB LPDDR4x + 16GB eMMC 5.1
JETSON | Xavier NX | DATA SHEET | DS-10184-001 | SUBJECT TO CHANGE | COPYRIGHT © 2014 – 2020 NVIDIA CORPORATION. ALL RIGHTS RESERVED. 3
Table of Contents
1.0 Functional Overview 5
1.1 Volta GPU .................................................................................................................................................... 5
1.2 Carmel CPU Complex ................................................................................................................................. 6
1.3 Memory Subsystem ..................................................................................................................................... 6
1.4 Memory ........................................................................................................................................................ 7
1.5 Video Input Interfaces .................................................................................................................................. 7
1.5.1 MIPI Camera Serial Interface (CSI) ............................................................................................... 7
1.5.2 Video Input (VI) ............................................................................................................................ 10
1.5.3 Image Signal Processor (ISP) ...................................................................................................... 10
1.6 Display Controller ...................................................................................................................................... 10
1.6.1 HDMI and DisplayPort Interfaces ................................................................................................. 12
1.6.2 Embedded DisplayPort (eDP) ...................................................................................................... 13
1.7 High-Definition Audio-Video Subsystem ................................................................................................... 14
1.7.1 Multi-Standard Video Decoder ..................................................................................................... 14
1.7.2 Multi-Standard Video Encoder ..................................................................................................... 15
1.7.3 JPEG Processing Block ............................................................................................................... 16
1.7.4 Video Image Compositor (VIC) .................................................................................................... 16
1.7.5 Audio Processing Engine (APE) .................................................................................................. 17
1.7.6 High Definition Audio (HDA) ........................................................................................................ 17
1.8 Interface Descriptions ................................................................................................................................ 17
1.8.1 SD/eMMC ..................................................................................................................................... 18
1.8.2 Universal Serial Bus (USB) .......................................................................................................... 18
1.8.3 PCI Express (PCIe) ...................................................................................................................... 19
1.8.4 Serial Peripheral Interface (SPI) .................................................................................................. 21
1.8.5 Universal Asynchronous Receiver/Transmitter (UART) .............................................................. 23
1.8.6 Controller Area Network (CAN) .................................................................................................... 24
1.8.7 Inter-Chip Communication (I
2
C) ................................................................................................... 25
1.8.8 Inter-IC Sound (I
2
S) ...................................................................................................................... 25
1.8.9 Gigabit Ethernet ........................................................................................................................... 27
1.8.10 Fan ............................................................................................................................................. 28
1.8.11 Pulse Width Modulator (PWM) ................................................................................................... 28
1.9 Deep Learning Accelerator (DLA) ............................................................................................................. 28
1.10 Programmable Vision Accelerator (PVA) ................................................................................................ 30
2.0 Power and System Management 31
2.1 Power Rails................................................................................................................................................ 31
2.2 Power Domains/Islands ............................................................................................................................. 32
2.3 Power Management Controller (PMC) ...................................................................................................... 32
2.4 Resets ........................................................................................................................................................ 32
2.5 PMIC_BBATT ............................................................................................................................................ 32
2.6 Power Sequencing .................................................................................................................................... 32
2.6.1 Power Up ..................................................................................................................................... 33
2.6.2 Power Down ................................................................................................................................. 33
2.7
Power States ............................................................................................................................................. 33
2.7.1 ON State ...................................................................................................................................... 34
2.7.2 OFF State ..................................................................................................................................... 34
2.7.3 SLEEP State ................................................................................................................................ 34
2.8 Thermal and Power Monitoring ................................................................................................................. 35
2.9 Overcurrent Throttling ................................................................................................................................ 35
3.0 Pin Definitions 36
3.1 Power-on Reset Behavior .......................................................................................................................... 36
3.2 Sleep Behavior .......................................................................................................................................... 36
3.3 GPIO .......................................................................................................................................................... 37
3.4 Pin List ....................................................................................................................................................... 38
Jetson Xavier NX System-on-Module
Volta GPU + Carmel CPU + 8GB LPDDR4x + 16GB eMMC 5.1
JETSON | Xavier NX | DATA SHEET | DS-10184-001 | SUBJECT TO CHANGE | COPYRIGHT © 2014 – 2020 NVIDIA CORPORATION. ALL RIGHTS RESERVED. 4
4.0 DC Characteristics 39
4.1 Operating and Absolute Maximum Ratings ............................................................................................... 39
4.2 Digital Logic ............................................................................................................................................... 40
5.0 Package Drawing and Dimensions 42
Jetson Xavier NX System-on-Module
Volta GPU + Carmel CPU + 8GB LPDDR4x + 16GB eMMC 5.1
JETSON | Xavier NX | DATA SHEET | DS-10184-001 | SUBJECT TO CHANGE | COPYRIGHT © 2014 – 2020 NVIDIA CORPORATION. ALL RIGHTS RESERVED. 5
1.0 Functional Overview
NVIDIA® Jetson Xavier™ NX brings AI supercomputer performance to the edge in a compact system-on-module (SOM) that’s
smaller than a credit card. Jetson Xavier NX is built around a low-power version of the NVIDIA Xavier SoC, combining the
NVIDIA Volta™ GPU architecture with 64-bit operating capability, integrated advanced multi-function video and image
processing, and NVIDIA Deep Learning Accelerators.
Compute performance up to 14 TOPS (at 10W) or 21 TOPS (at 15W) enables the Jetson Xavier NX to run multiple neural
networks in parallel and process data from multiple high-resolution sensors simultaneously. It also offers a unique combination
of performance and power advantages with a rich set of I/Os, from high-speed CSI and PCIe to low-speed I
2
Cs and GPIOs,
allowing embedded and edge computing devices that demand increased performance but are constrained by size, weight, and
power budgets.
1.1 Volta GPU
The Graphics Processing Cluster (GPC) is a dedicated hardware block for computing, rasterization, shading, and texturing of
most of the GPU’s core graphics functions. The GPC is comprised of Texture Processing Clusters (TPC), with each TPC
containing two Streaming Multiprocessor (SM) units, and a Raster Engine. The SM unit creates, manages, schedules, and
executes instructions from many threads in parallel. Raster operators (ROPs) continue to be aligned with L2 cache slices and
memory controllers. The SM geometry and pixel processing performance make it highly suitable for rendering advanced user
interfaces, while the efficiency of the Volta GPU enables this performance on devices with power-limited environments.
Each SM is partitioned into four separate processing blocks (referred to as SMPs), each SMP contains its own instruction
buffer, scheduler, CUDA cores, and Tensor cores. Inside each SMP, CUDA cores perform pixel/vertex/geometry shading and
physics/compute calculations, and each Tensor core provides a 4x4x4 matrix processing array to perform mixed-precision
fused multiply-add (FMA) mathematical operations. Texture units perform texture filtering and load/store units fetch and save
data to memory. Special Function Units (SFUs) handle transcendental and graphics interpolation instructions. Finally, the
PolyMorph Engine handles vertex fetch, tessellation, viewport transform, attribute setup, and stream output.
Features:
• End-to-end lossless compression
• Tile Caching
• Support for OpenGL 4.6, OpenGL ES 3.2, Vulkan 1.1
• Adaptive Scalable Texture Compression (ASTC) LDR profile supported
• CUDA support
• Iterated blend, ROP OpenGL-ES blend modes
• 2D BLIT from 3D class avoids channel switch
• 2D color compression
• Constant color render SM bypass
• 2x, 4x, 8x MSAA with color and Z compression
• Non-power of 2D and 3D textures, FP16 texture filtering
• FP16 shader support
• Geometry and Vertex attribute instancing
• Parallel pixel processing
• Early-z reject: Fast rejection of occluded pixels acts as multiplier on pixel shader and texture performance while
saving power and bandwidth
• Video protection region
• Power saving: Multiple levels of clock gating for linear scaling of power
Table 1: GPU Operation
Module
CUDA Cores
Tensor Cores
Power Mode
Operating Frequency per Core (up to)
Jetson Xavier NX
384
48
10W
800 MHz
15W
1100 MHz
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