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首页新版ampak正基AP62xx系列原理图_PIN TO PIN_REFERENCE DESIGN WO NFC
新版ampak正基AP62xx系列原理图_PIN TO PIN_REFERENCE DESIGN WO NFC
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更新于2023-05-25
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新版ampak正基AP62xx系列原理图_PIN TO PIN_REFERENCE DESIGN WO NFC 世联芯代理台湾正基WiFi模块 提供免费样品及技术支持 有需求请留言或私信
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A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
50 Ohm RF trace
WiFi ANT
Connected to HOST I/O 1V8
WLAN
BT/FM
AP6xxx Pin2Pin Reference Design Circuit
功功功功功功功功
Rated Current 1A
S_CLOCK
Brian
AP6XXX_PIN to PIN compatible design for 1V8 I/O
Trace width minimum >12mil
當當當
AP6181/AP6210/AP6212A/AP6234/AP6330/AP6335/AP6255
時
,
R21/R22/C18
不不不
,
模模
pin5,pin8
空空
當當當
AP6476
時
,R22/C18
需不不
, R21
不不不
FM RX
線線線線線線
AUDIO OUT
框
A
當當當
AP6210
時
,
框
A,B
皆皆皆皆皆
,
移移
R47/R48,
及框
C
器皆移移
.
接接接接接接
30
當當當
AP6181/AP6212A/AP6330/AP6335/AP6255/AP6234
時
,
框
B
皆皆皆皆皆
,
框
A,
框
C
器皆移移
,
接接接接接接
10,11
框
B
框
C
當當當
AP6476/AP6251
時
,
框
A,
框
B
移移皆移皆皆
.
接接接接接接
30
1.
注注注注注
AP6181/AP6212A/AP6330/AP6234
時
,
RL1/RL2
功電電電電電電電電
,
2.
注注注
AP6210/AP6476
時
,
RL1
功電電電電
,RL2
功電電電電電電電
,
3.
注注注
AP6335
時
, RL1
功電電電電電電電
,
RL2
功電電電電電電
SDIO3.0 (VIO
須須
1.8V)
4.
注注注
AP6255
時
, RL1/RL2
功電電電電
,
默默默默
1.8V for SDIO3.0
IN/OUT
電電需需
GPS ANT
(VBAT
功電電電
3.0V~4.8V,
供供功供供供
400mA)
RL1
RL2
當當當
AP6234/AP6255/AP6335
時
,
晶晶器皆
Y3
須須須須
37.4MHz.
當當當
AP6476/AP6251, R79
要要要
當當當
AP6212A
時
,R23
需不不
,R21,R22/C18
不不不
WL_HOST_WAKE
WL_REG_ON
32.768KHz
SDIO_D1
SDIO_CMD
UART_CTS_N
SDIO_D3
PCM_SYNC
PCM_OUT
WL_REG_ON
SDIO_D2
BT_HOST_WAKE
UART_RTS_N
PCM_CLK
WL_HOST_WAKE
PCM_IN
UART_RXD
SDIO_CLK
UART_TXD
SDIO_D0
BT_WAKE
BT_GPS_RST_N
BT_WAKE
BT_HOST_W AKE
HOST_UART_TXD
BT_GPS_RST_N
MCLK_IN
MCLK_IN
UART_RTS_N HOST_UART_CTS_N
PCM_CLK HOST_PCM_CLK
PCM_SYNC HOST_PCM_SYNC
PCM_IN HOST_PCM_OUT
PCM_OUT HOST_PCM_IN
UART_TXD HOST_UART_RXD
UART_RXD
HOST_UART_RTS_N
XTAL_IN XTAL_OUT
XTAL_IN
XTAL_OUT
MCLK_IN
FM_ANT
AUD_R
FM_ANTSDIO_VSEL
32.768KHz
SDIO_CMD
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
SDIO_CLK
EXTLNA_EN
AUD_L
UART_CTS_N
EXTLNA_EN
CLK_REQ
CLK_REQ
VDD_1V8
VDD_1V8
VDD_1V8
VBAT
VDD_1V8
VDD_1V8
VDD_1V8
VDD_1V8
VDD_1V8
AMPAK Technology co,Ltd
AMPAK Technology co,LtdAMPAK Technology co,Ltd
AMPAK Technology co,Ltd
Title:
Size:
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Appvd:
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of
1 1
2.4
C
Dora
<design name>
AMPAK Technology co,Ltd
AMPAK Technology co,LtdAMPAK Technology co,Ltd
AMPAK Technology co,Ltd
Title:
Size:
Directory:
Design:
File:
Appvd:
Rev:
Sheet:
Now date:
Present date:
of
1 1
2.4
C
Dora
<design name>
AMPAK Technology co,Ltd
AMPAK Technology co,LtdAMPAK Technology co,Ltd
AMPAK Technology co,Ltd
Title:
Size:
Directory:
Design:
File:
Appvd:
Rev:
Sheet:
Now date:
Present date:
of
1 1
2.4
C
Dora
<design name>
U1
AP6xxx
U1
AP6xxx
WL_BT_ANT
2
N_I2C_SCL
37
N_I2C_SDA
35
TX2
39
TCXO_IN
30
N_REG_PU
38
GND
36
TX1
40
WL_HOST_WAKE
13
GND
3
GND
1
GND
33
GND
31
BT_VIO/N_HOST_WAKE
8
PCM_OUT
25
PCM_CLK
26
PCM_IN
27
PCM_SYNC
28
VDDIO
22
LPO
24
SDIO_DATA_2
14
SDIO_DATA_0
18
SDIO_DATA_CLK
17
SDIO_DATA_CMD
16
SDIO_DATA_1
19
SDIO_DATA_3
15
VBAT
9
WL_REG_ON
12
BT_RST_N
34
FM_RX
4
N_WAKE
5
XTAL_IN
10
XTAL_OUT
11
GND
20
UART_TXD
42
UART_RXD
43
UART_RTS_N
41
UART_CTS_N
44
GPS_RF
32
BT_WAKE
6
BT_HOST_WAKE
7
VIN_LDO_OUT
21
VDD_TCXO
29
VIN_LDO
23
N_VDDSW PIO
45
N_VDDSW P_OUT
46
N_VDDSW P_IN
47
C16
4.7uF
C16
4.7uF
J1
AUDIO_JACK
J1
AUDIO_JACK
1
2
3
4
R71
0R
R71
0R
U8
MAX2659/BGU7005
U8
MAX2659/BGU7005
VCC
4
RFIN
3
GND
1
GND
2
ENABLE
5
RFOUT
6
U7
NL27WZU04 (SOT-363)
U7
NL27WZU04 (SOT-363)
IN A2
3
IN A1
1
GND
2
OUT Y2
4
Vcc
5
OUT Y1
6
R5 30KR5 30K
R81 10KR81 10K
R2 30KR2 30K
R47
0R/NP
R47
0R/NP
R12
100R
R12
100R
C24
1uF
C24
1uF
12
L5
6.8nH
L5
6.8nH
R79 0R/NPR79 0R/NP
X2
TCXO 26MHz (2520)
X2
TCXO 26MHz (2520)
VCC
4
OUT
3
GND
1
GND
2
C9
27pF
C9
27pF
R77
0R/NP
R77
0R/NP
C2
NP
C2
NP
R13
0R
R13
0R
Y3
26MHz (3225)
Y3
26MHz (3225)
1
1
2
2
3
3
4
4
R23 0RR23 0R
R10
560K
R10
560K
C27
10pF
C27
10pF
C28
470pF
C28
470pF
R3 30KR3 30K
FB1
75R-BEAD
FB1
75R-BEAD
C3
10pF
C3
10pF
C18 4.7uF/NPC18 4.7uF/NP
C25
33nF
C25
33nF
R48
0R/NP
R48
0R/NP
L3
4.7uH
L3
4.7uH
R4 30KR4 30K
C23
1uF
C23
1uF
12
R72
0R
R72
0R
R80 10KR80 10K
C15
4.7uF
C15
4.7uF
R6 0RR6 0R
R1 30KR1 30K
C22
1uF
C22
1uF
R59
0R/NP
R59
0R/NP
R82
10K/NC
R82
10K/NC
FB2
1.8K-BEAD
FB2
1.8K-BEAD
C11
27pF
C11
27pF
R22 0R/NPR22 0R/NP
C1
4.7uF
C1
4.7uF





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