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Apollo3 Blue Plus MCU Datasheet
Ultra-Low Power Apollo MCU Family
DS-A3P-0p3p0 Page 1 of 999 2019 Ambiq Micro, Inc.
All rights reserved.
Apollo3 Blue Plus
MCU Datasheet
Doc. ID: DS-A3P-0p3p0
Revision 0.3.0
October 2019
IMPORTANT NOTICE:
This datasheet includes content which is accurate to the
extent possible, but is preliminary and certain content may
not be fully validated.
Apollo3 Blue Plus MCU Datasheet
Ultra-Low Power Apollo MCU Family
DS-A3P-0p3p0 Page 2 of 999 2019 Ambiq Micro, Inc.
All rights reserved.
Features
Ultra-low supply current:
- 6 µA/MHz executing from FLASH or RAM at 3.3 V
- 1 µA deep sleep mode (BLE Off) with RTC at 3.3 V
High-performance ARM Cortex-M4 Processor
- 48 MHz nominal clock frequency, with 96 MHz high perfor-
mance TurboSPOT™ Mode
- Floating point unit
- Memory protection unit
- Wake-up interrupt controller with 32 interrupts
Integrated Bluetooth
1
5 low-energy module
- RF sensitivity: -93 dBm (typical)
- TX: 3 mA @ 0 dBm, RX: 3 mA
- Tx peak output power: 4.0 dBm (max)
Ultra-low power memory:
- Up to 2 MB of flash memory for code/data
- Up to 768 KB of low leakage RAM for code/data
- 16 kB 2-way Associative/Direct-Mapped Cache
Ultra-low power interface for on- and off-chip sensors:
- 14 bit ADC at up to 1.2 MS/s, 15 selectable input channels
available
- Voltage Comparator
- Temperature sensor with +/- 3ºC accuracy after calibration
ISO7816 Secure interface
Flexible serial peripherals:
- 1x 2/4/8-bit and 2x 2/4-bit SPI master interfaces (MSPIs)
- 6x I
2
C/SPI masters for peripheral communication
- I
2
C/SPI slave for host communications
- 2x UART modules with 32-location Tx and Rx FIFOs
- PDM for mono and stereo audio microphone
- 1x I
2
S slave for PDM audio pass-through
Rich set of clock sources:
- 32.768 kHz XTAL oscillator
- Low frequency RC oscillator – 1.024 kHz
- High frequency RC oscillator – 48/96 MHz
- RTC based on Ambiq’s AM08X5/18X5 families
Wide operating range: 1.755-3.63 V, –40 to 85°C
Compact package:
- 5.3 x 4.3 x 0.8 mm, 108-ball BGA with 74 GPIO
1. The Bluetooth® word mark and logos are registered trademarks
owned by the Bluetooth SIG, Inc. and any use of such marks is under
license. Other trademarks and trade names are those of their respec-
tive owners.
Applications
Description
The Apollo MCU Family is an ultra-low power, highly integrated
microcontroller platform based on Ambiq Micro’s patented Sub-
threshold Power Optimized Technology (SPOT™) and designed
for battery-powered and portable, mobile devices. The Apollo3
Blue Plus MCU sets a new standard in energy efficiency for bat-
tery-powered devices with an integrated ARM Cortex-M4 proces-
sor with Floating Point Unit and TurboSPOT™ increasing the
computational capabilities of the ARM Cortex M4F core to 96MHz
while lowering the active power consumption to <6uA/MHz. This
combination dramatically reduces energy consumption while still
enabling abundant application processing power to add greater
capability and extended life to battery operated devices.
The Apollo3 Blue brings several new features to Ambiq’s SPOT-
based Apollo MCU Family including an integrated DMA engine,
QSPI interface and advanced stepper motor control for ultra-low
power analog watch hand management. The Apollo3 Blue also
forms the core of Ambiq’s Voice-on-SPOT™ reference platform
making it the perfect device for always-on voice assistant integra-
tion and command recognition to battery-powered devices. The
Apollo3 Blue provides a dedicated second core for the ultra-low
power BLE5 connectivity platform providing superior RF through-
put and leaving plenty of resources available for user applications.
The Apollo3 Blue Plus adds two additional MSPI modules (3 total),
and increases the external memory execute-in-place (XiP)
aperture from 64MB to 96MB (32MB/ MSPI instance). Additionally,
internal FLASH increases from 1MB to 2MB, SRAM from 384KB to
768KB (TCM size remains at 64KB) and the GPIO count increases
from 50 to 74.
▪ Voice-on-SPOT™ compatible for always-listening keyword
detect, audio command recognition and voice assistant integra-
tion in battery-powered devices including:
- Bluetooth headsets, earbuds, and truly wireless earbuds
- Remote and Gaming Controls
- Smart home
▪ Wearables including smart watches and fitness/activity trackers
▪ Hearing aids, Digital Health Monitoring and Sensing Devices
▪ Smart Home Automation, Security and Lighting control applica-
tions
Ambiq Micro
Apollo3
MCU
Host
Processor
(optional)
SPI/I
2
C
Slave
Port
SPI/I
2
C Master,
UART
GPS / WiFi
Magnetometer
with Digital
Output
Gyroscope
with Digital
Output
Accelerometer
with Digital
Output
Typical Application Circuit for the Apollo3 MCU
External Flash
Multi-bit
SPI
Display
Apollo3 Blue Plus MCU Datasheet
Ultra-Low Power Apollo MCU Family
DS-A3P-0p3p0 Page 3 of 999 2019 Ambiq Micro, Inc.
All rights reserved.
Table of Content
1. Apollo3 Blue Plus MCU Package Pins .............................................................................. 49
1.1 Pin Configuration ....................................................................................................... 49
1.2 Pin Connections ......................................................................................................... 49
2. System Core ....................................................................................................................... 73
3. MCU Core Details ............................................................................................................. 75
3.1 Interrupts .................................................................................................................... 76
3.2 Memory Map ............................................................................................................. 79
3.3 Memory Protection Unit (MPU) ................................................................................ 83
3.4 System Busses ............................................................................................................ 84
3.5 Power Management ................................................................................................... 85
3.5.1 Cortex-M4 Power Modes .................................................................................. 85
3.5.2 System Power Modes ........................................................................................ 86
3.5.3 Power Control ................................................................................................... 89
3.6 Debug Interfaces ...................................................................................................... 107
3.6.1 Debugger Attachment ..................................................................................... 107
3.6.2 Instrumentation Trace Macrocell (ITM) ......................................................... 107
3.6.3 Trace Port Interface Unit (TPIU) .................................................................... 107
3.6.4 Faulting Address Trapping Hardware ............................................................. 107
3.7 ITM Registers .......................................................................................................... 108
3.7.1 Register Memory Map .................................................................................... 109
3.7.2 ITM Registers ................................................................................................. 111
3.8 MCUCTRL Registers .............................................................................................. 137
3.8.1 Register Memory Map .................................................................................... 138
3.8.2 MCUCTRL Registers ..................................................................................... 140
3.9 Memory Subsystem ................................................................................................. 173
3.9.1 Features ........................................................................................................... 174
3.9.2 Functional Overview ....................................................................................... 174
3.9.3 Flash Cache ..................................................................................................... 175
3.9.4 SRAM Interface .............................................................................................. 193
4. Security ............................................................................................................................ 195
4.1 Functional Overview ................................................................................................ 195
4.2 Secure Boot .............................................................................................................. 195
4.3 Secure OTA ............................................................................................................. 195
4.4 Secure Key Storage .................................................................................................. 196
4.5 External Flash Inline Encrypt/Decrypt .................................................................... 196
5. DMA ................................................................................................................................ 197
5.1 Functional Overview ................................................................................................ 197
5.1.1 General Usage ................................................................................................. 197
5.1.2 Auto Power Down .......................................................................................... 198
5.1.3 Priority ............................................................................................................ 198
5.1.4 Hardware Handshake / Hardware Triggering ................................................. 198
6. BLE Module .................................................................................................................... 199
6.1 Functional Overview ................................................................................................ 199
6.1.1 Introduction ..................................................................................................... 199
Apollo3 Blue Plus MCU Datasheet
Ultra-Low Power Apollo MCU Family
DS-A3P-0p3p0 Page 4 of 999 2019 Ambiq Micro, Inc.
All rights reserved.
6.1.2 Main Features ................................................................................................. 199
6.2 Functional Description ............................................................................................. 200
6.2.1 Data Transfers ................................................................................................. 200
6.3 BLEIF Registers ...................................................................................................... 201
6.3.1 Register Memory Map .................................................................................... 202
6.3.2 BLEIF Registers ............................................................................................. 204
7. MSPI Master Module ....................................................................................................... 237
7.1 Functional Overview ................................................................................................ 237
7.2 Configuration ........................................................................................................... 238
7.3 PIO Operations ........................................................................................................ 239
7.4 DMA Operations ...................................................................................................... 240
7.5 Execute in Place (XIP) Operations .......................................................................... 241
7.5.1 XIPMM Operation .......................................................................................... 241
7.5.2 Optimized XIP Addressing ............................................................................. 241
7.5.3 Micron XIP Support ........................................................................................ 242
7.6 Command Queueing (CQ) ....................................................................................... 242
7.6.1 Command Queue Data Format ....................................................................... 242
7.6.2 CQ Interrupts .................................................................................................. 243
7.6.3 Pausing CQ Operations ................................................................................... 244
7.6.4 Using the CQ Index registers .......................................................................... 245
7.6.5 MSPI and IOM Intercommunication .............................................................. 246
7.7 Data Scrambling ...................................................................................................... 246
7.8 Auto Power Down ................................................................................................... 246
7.9 Pad Configuration and Enables ................................................................................ 246
7.9.1 Internal Pin Muxing Options .......................................................................... 248
7.9.2 MSPI Pin Timing Board/Package Considerations .......................................... 249
7.10 MSPI Registers ...................................................................................................... 250
7.10.1 Register Memory Map .................................................................................. 251
7.10.2 MSPI Registers ............................................................................................. 254
8. I2C/SPI Master Module ................................................................................................... 288
8.1 Functional Overview ................................................................................................ 288
8.1.1 Main Features ................................................................................................. 289
8.2 Functional Description ............................................................................................. 289
8.2.1 Power Control ................................................................................................. 289
8.2.2 Clocking and Resets ........................................................................................ 289
8.2.3 FIFO ................................................................................................................ 292
8.2.4 Data Alignment ............................................................................................... 292
8.2.5 Transaction Initiation ...................................................................................... 294
8.2.6 Command Queue ............................................................................................ 295
8.3 Programmer’s Reference ......................................................................................... 298
8.4 Interface Clock Generation ...................................................................................... 298
8.5 Command Operation ................................................................................................ 299
8.6 FIFO ......................................................................................................................... 300
8.7 I2C Interface ............................................................................................................ 300
8.7.1 Bus Not Busy .................................................................................................. 300
8.7.2 Start Data Transfer .......................................................................................... 301
Apollo3 Blue Plus MCU Datasheet
Ultra-Low Power Apollo MCU Family
DS-A3P-0p3p0 Page 5 of 999 2019 Ambiq Micro, Inc.
All rights reserved.
8.7.3 Stop Data Transfer .......................................................................................... 301
8.7.4 Data Valid ....................................................................................................... 301
8.7.5 Acknowledge .................................................................................................. 301
8.7.6 I2C Slave Addressing ..................................................................................... 301
8.7.7 I2C Offset Address Transmission ................................................................... 302
8.7.8 I2C Write Operation with Address Offset ...................................................... 302
8.7.9 I2C Read Operation with Address Offset ....................................................... 303
8.7.10 I2C Write Operation with No Address Offset .............................................. 303
8.7.11 I2C Read Operation with No Address Offset ............................................... 304
8.7.12 Holding the Interface with CONT ................................................................ 304
8.7.13 I2C Multi-master Arbitration ........................................................................ 304
8.8 SPI Operations ......................................................................................................... 304
8.8.1 SPI Configuration ........................................................................................... 304
8.8.2 SPI Slave Addressing ...................................................................................... 305
8.8.3 SPI Write with Address Offset ....................................................................... 305
8.8.4 SPI Read with Address Offset ........................................................................ 305
8.8.5 SPI Write with No Address Offset ................................................................. 306
8.8.6 SPI Read with No Address Offset .................................................................. 306
8.8.7 SPI 3-wire Mode ............................................................................................. 307
8.8.8 Complex SPI Operations ................................................................................ 307
8.8.9 SPI Polarity and Phase .................................................................................... 307
8.9 Apollo3 Blue Plus MCUBit Orientation .................................................................. 308
8.10 SPI Flow Control ................................................................................................... 308
8.11 Minimizing Power ................................................................................................. 310
8.12 IOM Registers ........................................................................................................ 311
8.12.1 Register Memory Map .................................................................................. 312
8.12.2 IOM Registers ............................................................................................... 317
9. I2C/SPI Slave Module ..................................................................................................... 354
9.1 Functional Overview ................................................................................................ 354
9.2 Local RAM Allocation ............................................................................................ 354
9.3 Direct Area Functions .............................................................................................. 355
9.4 FIFO Area Functions ............................................................................................... 358
9.5 Rearranging the FIFO .............................................................................................. 359
9.6 Interface Interrupts ................................................................................................... 360
9.7 Command Completion Interrupts ............................................................................ 361
9.8 Host Address Space and Registers ........................................................................... 361
9.9 I2C Interface ............................................................................................................ 361
9.9.1 Bus Not Busy .................................................................................................. 362
9.9.2 Start Data Transfer .......................................................................................... 362
9.9.3 Stop Data Transfer .......................................................................................... 362
9.9.4 Data Valid ....................................................................................................... 362
9.9.5 Acknowledge .................................................................................................. 362
9.9.6 Address Operation .......................................................................................... 363
9.9.7 Offset Address Transmission .......................................................................... 363
9.9.8 Write Operation .............................................................................................. 364
9.9.9 Read Operation ............................................................................................... 364
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