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DDR2 JEDEC标准
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JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD79-2F
November 2009
JEDEC
STANDARD
DDR2 SDRAM SPECIFICATION
(Revision of JESD79-2E)
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal Counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization, there are procedures whereby a JEDEC standard or
publication mya be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or
www.jedec.org.
Published by
©JEDEC Solid State Technology Association 2009
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Arlington, VA 22201
This document may be downloaded free of charge, however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
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This document is copyrighted by the Electronic Industries Alliance and may not be
reproduced without permission.
Organizations may obtain permission to reproduce a limited number of copies
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JEDEC Solid State Technology Association
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or call (703) 907-7559
This page intentionally left blank.
JEDEC Standard No. 79-2F
Contents
1 Scope ................................................................................................................................................. 1
2 Package ballout & addressing ......................................................................................................... 2
2.1 DDR2 SDRAM package ballout ...................................................................................................... 2
2.2 Quad-stacked/quad-die DDR2 SDRAM internal rank associations .............................................. 11
2.3 Input/output functional description ................................................................................................ 13
2.4 DDR2 SDRAM addressing ............................................................................................................ 14
3 Functional description ................................................................................................................... 16
3.1 Simplified state diagram ................................................................................................................ 16
3.2 Basic functionality ......................................................................................................................... 16
3.3 Power-up and initialization ............................................................................................................ 16
3.3.1 Power-up and initialization sequence ........................................................................................ 17
3.4 Programming the mode and extended mode registers ................................................................. 18
3.4.1 DDR2 SDRAM mode register (MR) ........................................................................................... 18
3.4.2 DDR2 SDRAM extended mode registers (EMR(#)) ................................................................... 19
3.4.3 Off-chip driver (OCD) impedance adjustment ............................................................................ 24
3.4.4 ODT (on-die termination) ........................................................................................................... 27
3.4.5 ODT related timings ................................................................................................................... 27
3.5 Bank activate command ................................................................................................................ 32
3.6 Read and write access modes ...................................................................................................... 32
3.6.1 Posted CAS ............................................................................................................................... 32
3.6.2 Burst mode operation ................................................................................................................ 34
3.6.3 Burst read command ................................................................................................................. 34
3.6.4 Burst write operation .................................................................................................................. 37
3.6.5 Write data mask ......................................................................................................................... 40
3.7 Precharge operation ..................................................................................................................... 41
3.7.1 Burst read operation followed by precharge .............................................................................. 42
3.7.2 Burst write followed by precharge .............................................................................................. 44
3.8 Auto precharge operation ............................................................................................................. 45
3.8.1 Burst read with auto precharge .................................................................................................. 46
3.8.2 Burst write with auto precharge ................................................................................................. 48
3.9 Refresh command ......................................................................................................................... 49
3.10 Self refresh operation .................................................................................................................... 50
3.11 Power-down .................................................................................................................................. 51
3.12 Asynchronous CKE LOW event .................................................................................................... 55
3.13 Input clock frequency change during precharge power down ....................................................... 56
3.14 SSC (Spread Spectrum Clocking) ................................................................................................ 57
3.14.1 Terms and definitions ................................................................................................................ 57
3.14.2 SSC (Spread Spectrum Clocking) Criteria ................................................................................. 57
3.14.3 Allowed SSC band .................................................................................................................... 57
3.15 No operation command ................................................................................................................. 57
3.16 Deselect command ....................................................................................................................... 57
4 Truth tables ..................................................................................................................................... 58
4.1 Command truth table .................................................................................................................... 58
4.2 Clock enable truth table. ............................................................................................................... 59
4.3 Data mask truth table. ................................................................................................................... 60
5 Absolute maximum DC ratings ...................................................................................................... 61
6 AC & DC operating conditions ...................................................................................................... 62
Annex A (informative) Differences between JESD79-2F and JESD79-2E ..................................... 109
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