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VR12/IMVP7 Pulse Width Modulation

This document defines the PWM control chip features for the VRD12, VRM12 & IMVP7 CPU dc-dc converters used in Intel platforms. VR12/IMVP7 includes a Serial VID (SVID) interface; benefits of SVID can be seen in reduced number of required pins and 2 way communications between the CPU and VR. Future platform power delivery design guidelines will contain the actual platform implementations for IMVP7 or VRD12 in mobility, desktop and server market segments and takes precedent over targets shown in this document.
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Document Number: 397113
VR12/IMVP7 Pulse Width Modulation
(PWM) Specification
December 2009
Revision 1.4
Intel Confidential

Introduction
2 Intel Confidential CDI/IBL: 397113
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Introduction
CDI/IBL: 397113 Intel Confidential 3
Contents
1 Introduction .....................................................................................................9
1.1 Methodology, definition changes from VR11.x.............................................9
1.2 Terminology ........................................................................................10
2 Market Segment Definitions..............................................................................14
2.1 Mobility (Notebook, Netbook, Nettop) Market Segments.............................14
2.2 Desktop Market Segment ......................................................................14
2.3 Server Market Segment.........................................................................15
2.4 For dual output VR, the following features are common: ............................15
2.5 Summary of market segment requirements (X=required, O=optional) ......... 16
3 VID Operating Features ...................................................................................19
3.1 SerialVID (SVID) Overview ....................................................................19
3.2 SVID DC Electrical Parameters Required ..............................................19
3.3 VCLK Timing Parameters Required ......................................................20
3.4 Data Sampling and Timing analysis......................................................... 22
3.4.1 Silicon Validation, CRB, Electrical Validation Platforms Bus Timing all
market segments ....................................................................
22
3.4.2 OEM Production Platform Bus Timing All Market Segments ............23
3.5 Addressing required all segments ..........................................................24
3.6 VID Table Required all segments ........................................................... 25
3.7 Dynamic Voltage Identification (D-VID) REQUIRED all segments ................. 37
3.7.1 Dynamic VID Slew rates- Mobility segment ................................. 38
3.7.2 Dynamic VID Slew rates – Desktop segment ...............................38
3.7.3 Dynamic VID slew rates - Server segment ..................................38
3.7.4 Voltage Settled function Required all segments...........................39
3.8 VR Power States (PS) Required all segments ............................................41
3.8.1 Power State Exit Latencies........................................................43
3.9 VR Data Registers ................................................................................43
3.9.1 ICC max (21h) Required all segments..............................43
3.9.2 Temp max (22h) Optional IMVP/Notebook segment, Required
Server segments .....................................................................
43
3.9.3 DC_LL or AVP (23h) Required all segments ..............................44
3.9.4 Slew Rate Fast (24h) Required ................................................44
3.9.5 Slew Rate Slow (25h) Required ................................................. 44
3.9.6 Vboot (26h) Required all segments ............................................44
3.9.7 VR tolerance (27h) Optional...................................................... 45
3.9.8 Current Calibration offset (28h) Optional ...................................45
3.9.9 Temperature Calibration offset (29h) Optional ............................45
3.10 VR operating Registers..........................................................................45
3.10.1 Vout-max (30h) Required all segments................................... 45
3.10.2 Temperature zone (12h) Required all segments ........................ 46
3.10.3 Iout, Output Current (15h) Required Desktop, Server segments,
Optional Mobility .....................................................................
46
3.10.4 VR Temperature (17h) Optional...............................................49

Introduction
4 Intel Confidential CDI/IBL: 397113
3.10.5 Output Voltage (16h) Optional ................................................ 49
3.10.6 Offset (33h) Required all segments .........................................50
4 Start up sequence Required all segments .......................................................51
4.1 VR_Enable REQUIRED all segments........................................................54
4.2 Under Voltage Lock Out (UVLO) REQUIRED all segments...........................54
4.3 Soft Start (SS) Optional all segments .................................................... 55
4.4 Vboot .................................................................................................55
5 General Operation...........................................................................................56
5.1 # phases EXPECTED ............................................................................56
5.2 Phase Current Sense Input Expected ....................................................56
5.3 Error Amp specification: EXPECTED.........................................................56
5.4 PWM Operating Frequency EXPECTED...................................................... 56
5.5 Differential Remote Sense Input REQUIRED ............................................57
5.6 Output Indicators .................................................................................57
5.6.1 VR_Ready REQUIRED..............................................................57
5.6.2 Thermal Monitoring AKA VR_Hot# REQUIRED all segments.........58
5.7 Output Protection .................................................................................60
5.7.1 Over-Voltage Protection (OVP) PROPOSED ................................ 60
5.7.2 Over-Current Protection (OCP) PROPOSED ................................60
5.7.3 Catastrophic Fault Detect – Expected for Server Segment .............61
5.8 VR Tolerance .......................................................................................61
5.8.1 Load Line Definitions REQUIRED all segments.............................61
5.8.2 Voltage Tolerance REQUIRED all segments................................62
5.8.3 Load Line Thermal Compensation REQUIRED all segments ............63
5.9 No load operation required all segments .................................................63
6 Design collateral .............................................................................................64
6.1 Demo, test board requirement (VRTB) REQUIRED .....................................64
6.2 Computer models REQUIRED .................................................................64
6.3 VR Tolerance Band calculator REQUIRED .................................................64
7 SMBUS/PMBUS support for Servers or extreme edition desktop – Optional ..............65

Introduction
CDI/IBL: 397113 Intel Confidential 5
Figures
Figure 1 Definition of Vhysteresis in table 3 ........................................................20
Figure 2. Measurement Points for VCLK High, Low, Rise and Fall Time, Tperiod ........21
Figure 3. Serial VID Bit Transfer........................................................................22
Figure 4. Clock and Data sample CPU driving timing definitions (all market segments)
23
Figure 5. Clock and Data sample VR driving timing definitions (all market segments) 24
Figure 6 VR Settled example moving from lower to higher VID & VR settled ............40
Figure 7 Example of Dynamic VID and VR_Settled, Alert# function ........................41
Figure 8 Allowable Power State operating window................................................42
Figure 9 VR start up timings .............................................................................52
Figure 10. Typical Example Platform Startup Sequence Note Vboot=0V on each rail.53
Figure 11 Thermal zone and detection encoding ..................................................59
Figure 12 Alert#, Thermal_Alert & VR_HOT# behavior. ........................................59
Figure 13. VR tolerance definitions (neglecting overshoot relief) ............................62
Tables
Table 1. Feature Support Terminology................................................................10
Table 2. Glossary ............................................................................................10
Table 3. VR DC Electrical Parameters .................................................................19
Table 4 VR AC Electrical parameters ..................................................................20
Table 5. VCLK AC Timing Parameters .................................................................21
Table 6 Address definitions per socket................................................................25
Table 7 VID range and power state support ........................................................27
Table 8: VID Table ..........................................................................................27
Table 9 VR Start UP Timings ............................................................................52
Table 10 Enable pin voltage levels .....................................................................54
Table 11, Open Drain Output Signal Specifications (VR_Ready).............................57
Table 12 Minimum Recommended PMBUS command set .......................................65
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