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RTL8380M_RTL8382M_RTL8382L_Datasheet_Draft_v0.7.pdf
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RTL8380M_RTL8382M_RTL8382L_Datasheet_Draft_v0.7.pdf
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RTL8380M-CG
MULTI-LAYER MANAGED 18*10/100/
RTL8382M-CG
MULTI-LAYER MANAGED 28*10/100/
RTL8382L-CG
UN-MANAGED 26*10/100/1000M-PORT SWITCH CONTROLLERS
DRAFT DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 0.7
20 February. 2013
Track ID:
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8380M/RTL8382M/RTL8382L
Datasheet
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers ii Track ID: Rev. 0.
7
COPYRIGHT
©2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document provides detailed user guidelines to achieve the best performance when implementing the
Realtek Ethernet Switch Controllers.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary
0.1 2012/05/12 Initial draft.
0.2 2012/08/08 Updated.
0.3 2012/09/18 Revised the pin description error for MEM_TYPE[1:0] on table 14, 30 and 44.
0.4 2012/10/18
Add 11.4 AC characteristics;
0.5 2013/01/24
Update RTL8382L pin assignment;
Add uart1 interface description;
Add GPIO[14:11] and GPO10 description;
Modify the ddr2 and spi flash timing Characteristics;
Add ddr3 timing Characteristics;
0.6 2013/02/20 Modify the description for CLK_M_EE[1:0];
0.7 2013/05/02 Modify the AC Characteristic of QSGMII VTX-DIFFp-p and VRX-DIFFp-p;
Modify the operating range of the DVDDL, AVDDL, SVDDL, AVDDL_PLL,
PLLVDDL and VDDIO.
RTL8380M/RTL8382M/RTL8382L
Datasheet
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers iii Track ID: Rev. 0.
7
Table of Contents
1.
GENERAL DESCRIPTION..............................................................................................................................................1
2.
FEATURES.........................................................................................................................................................................3
3.
SYSTEM APPLICATIONS...............................................................................................................................................3
3.1.
RTL8380M:
M
ANAGED
16*1000M
UTP+2*1000B
ASE
-X
S
WITCH
............................................................................3
3.2.
RTL8382M:
M
ANAGED
28*1000M
S
WITCH VIA
RTL8218B
PHY .............................................................................4
3.3.
RTL8382M:
M
ANAGED
20*1000M
UTP+4*1000M
C
OMBO
S
WITCH
........................................................................5
3.4.
RTL8382M/RTL8382L:
M
ANAGED
/U
NMANAGED
24*1000M
UTP+2*1000B
ASE
-X
S
WITCH
..................................6
4.
BLOCK DIAGRAMS.........................................................................................................................................................7
4.1.
RTL8380M
B
LOCK
D
IAGRAM
.....................................................................................................................................7
4.2.
RTL8382M
B
LOCK
D
IAGRAM
.....................................................................................................................................8
4.3.
RTL8382L
B
LOCK
D
IAGRAM
......................................................................................................................................9
5.
PIN ASSIGNMENTS AND DESCRIPTION (RTL8380M)..........................................................................................10
5.1.
P
IN
A
SSIGNMENTS
F
IGURE
(RTL8380M) ..................................................................................................................10
5.2.
P
ACKAGE
I
DENTIFICATION
.........................................................................................................................................11
5.3.
P
IN
A
SSIGNMENTS
T
ABLE
C
ODES
(RTL8380M)........................................................................................................11
5.4.
P
IN
A
SSIGNMENTS
T
ABLE
(RTL8380M)....................................................................................................................11
5.5.
P
IN
D
ESCRIPTIONS
(RTL8380M)...............................................................................................................................16
5.5.1.
1000M Ethernet PHY MDI Interface Pins............................................................................................................16
5.5.2.
SGMII Interface Pins............................................................................................................................................17
5.5.3.
RSGMII Interface Pins.........................................................................................................................................18
5.5.4.
QSGMII Interface Pins.........................................................................................................................................18
5.5.5.
1000Base-X/100Base-FX Interface Pins..............................................................................................................18
5.5.6.
DDR1/2 SDRAM Interface Pins ...........................................................................................................................19
5.5.7.
DDR3 SDRAM Interface Pins ..............................................................................................................................19
5.5.8.
Master Mode-SPI Flash Interface Pins................................................................................................................20
5.5.9.
UART Interface Pins.............................................................................................................................................20
5.5.10.
LED Interface Pins..........................................................................................................................................21
5.5.11.
GPIO Interface Pins........................................................................................................................................21
5.5.12.
EJTAG Interface Pins......................................................................................................................................21
5.5.13.
Configuration Strapping Pins..........................................................................................................................22
5.5.14.
Miscellaneous Interface Pins...........................................................................................................................23
5.5.15.
Power and GND Pins ......................................................................................................................................24
6.
PIN ASSIGNMENTS AND DESCRIPTION (RTL8382M)..........................................................................................25
6.1.
P
IN
A
SSIGNMENTS
F
IGURE
(RTL8382M) ..................................................................................................................25
6.2.
P
ACKAGE
I
DENTIFICATION
.........................................................................................................................................25
6.3.
P
IN
A
SSIGNMENTS
T
ABLE
C
ODES
(RTL8382M)........................................................................................................26
6.4.
P
IN
A
SSIGNMENTS
T
ABLE
(RTL8382M)....................................................................................................................26
6.5.
P
IN
D
ESCRIPTION
(RTL8382M).................................................................................................................................30
6.5.1.
1000M Ethernet PHY MDI Interface Pins............................................................................................................30
6.5.2.
SGMII Interface Pins............................................................................................................................................32
6.5.3.
RSGMII Interface Pins.........................................................................................................................................32
6.5.4.
QSGMII Interface Pins.........................................................................................................................................32
6.5.5.
1000Base-X/100Base-FX Interface Pins..............................................................................................................33
6.5.6.
DDR1/2 SDRAM Interface Pins ...........................................................................................................................33
6.5.7.
DDR3 SDRAM Interface Pins ..............................................................................................................................34
6.5.8.
Master Mode-SPI Flash Interface Pins................................................................................................................35
6.5.9.
UART Interface Pins.............................................................................................................................................35
6.5.10.
LED Interface Pins..........................................................................................................................................35
RTL8380M/RTL8382M/RTL8382L
Datasheet
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers iv Track ID: Rev. 0.
7
6.5.11.
GPIO Interface Pins........................................................................................................................................35
6.5.12.
EJTAG Interface Pins......................................................................................................................................36
6.5.13.
Configuration Strapping Pins..........................................................................................................................36
6.5.14.
Miscellaneous Interface Pins...........................................................................................................................37
6.5.15.
Power and GND Pins ......................................................................................................................................38
7.
PIN ASSIGNMENTS AND DESCRIPTION (RTL8382L)...........................................................................................39
7.1.
P
IN
A
SSIGNMENTS
F
IGURE
(RTL8382L) ...................................................................................................................39
7.2.
P
ACKAGE
I
DENTIFICATION
.........................................................................................................................................40
7.3.
P
IN
A
SSIGNMENTS
T
ABLE
C
ODES
(RTL8382L).........................................................................................................40
7.4.
P
IN
A
SSIGNMENTS
T
ABLE
(RTL8382L).....................................................................................................................40
7.5.
P
IN
D
ESCRIPTIONS
(RTL8382L)................................................................................................................................44
7.5.1.
1000M Ethernet PHY MDI Interface Pins............................................................................................................44
7.5.2.
SGMII Interface Pins............................................................................................................................................46
7.5.3.
QSGMII Interface Pins.........................................................................................................................................46
7.5.4.
1000Base-X/100Base-FX Interface Pins..............................................................................................................46
7.5.5.
Master Mode-SPI Flash Interface Pins................................................................................................................47
7.5.6.
UART Interface Pins.............................................................................................................................................47
7.5.7.
LED Interface Pins...............................................................................................................................................47
7.5.8.
GPIO Interface Pins.............................................................................................................................................48
7.5.9.
Configuration Strapping Pins...............................................................................................................................48
7.5.10.
Miscellaneous Interface Pins...........................................................................................................................49
7.5.11.
Power and GND Pins ......................................................................................................................................50
8.
SWITCH FUNCTION DESCRIPTION.........................................................................................................................51
8.1.
H
ARDWARE
R
ESET AND
S
OFTWARE
R
ESET
................................................................................................................51
8.1.1.
Hardware Reset....................................................................................................................................................51
8.1.2.
Software Reset......................................................................................................................................................51
8.2.
C
RYSTAL
....................................................................................................................................................................51
8.3.
IEEE
802.3
AZ
E
NERGY
E
FFICIENT
E
THERNET
(EEE) ................................................................................................51
8.4.
L
AYER
2
L
EARNING AND
F
ORWARDING
.....................................................................................................................52
8.4.1.
Forwarding...........................................................................................................................................................52
8.4.2.
Learning ...............................................................................................................................................................52
8.4.3.
DA/SA Block.........................................................................................................................................................52
8.5.
PORT ISOLATION ........................................................................................................................................................53
8.6.
IEEE
802.3
X
F
LOW
C
ONTROL
...................................................................................................................................54
8.7.
H
ALF
D
UPLEX
B
ACKPRESSURE
..................................................................................................................................55
8.7.1.
Collision-Based Backpressure (Jam Mode) .........................................................................................................55
8.7.2.
Carrier-Based Backpressure (I.e., Defer Mode) ..................................................................................................55
8.8.
L
AYER
2
M
ULTICAST AND
IP
M
ULTICAST
.................................................................................................................56
8.9.
IEEE
802.1
D
/1
W
/1
S
(STP/RSTP/MSTP)...................................................................................................................56
8.10.
IEEE
802.1
P AND
IEEE
802.1Q
(VLAN) ..................................................................................................................57
8.11.
IEEE
802.1X
(N
ETWORK
A
CCESS
C
ONTROL
)............................................................................................................58
8.12.
R
ESERVED
M
ULTICAST
A
DDRESS
H
ANDLING
............................................................................................................59
8.13.
L
AYER
2
T
RAFFIC
S
UPPRESSION
(S
TORM
C
ONTROL
) .................................................................................................60
8.14.
PIE
(P
ACKET
I
NSPECTION
E
NGINE
)............................................................................................................................60
8.14.1.
Ingress ACL.....................................................................................................................................................60
8.15.
I
NPUT
B
ANDWIDTH
C
ONTROL AND
ACL
T
RAFFIC
M
ETER
.........................................................................................61
8.15.1.
Input Bandwidth Control.................................................................................................................................61
8.15.2.
ACL Traffic Meter............................................................................................................................................61
8.16.
IEEE
802.3
AD
L
INK
A
GGREGATION
P
ROTOCOL
........................................................................................................61
8.17.
IEEE
802.1
AD
VLAN
S
TACKING
...............................................................................................................................62
8.18.
Q
UALITY OF
S
ERVICE
(Q
O
S)......................................................................................................................................63
8.19.
P
ACKET
S
CHEDULING
(WRR
AND
WFQ)...................................................................................................................64
8.20.
P
ACKET
D
ROP
A
LGORITHM
(TD)...............................................................................................................................65
RTL8380M/RTL8382M/RTL8382L
Datasheet
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers v Track ID: Rev. 0.
7
8.21.
E
GRESS
P
ACKET
R
EMARKING
....................................................................................................................................65
8.22.
I
NGRESS AND
E
GRESS
P
ORT
M
IRROR
.........................................................................................................................65
8.22.1.
Remote Mirror (RAPAN).................................................................................................................................66
8.23.
M
ANAGEMENT
I
NFORMATION
B
ASE
(MIB) ...............................................................................................................67
8.24.
NIC
AND
CPU
T
AG
F
ORWARDING
.............................................................................................................................67
8.25.
I
NDIRECT
T
ABLE
A
CCESS
...........................................................................................................................................68
8.26.
E
XTERNAL
PHY
R
EGISTER
A
CCESS
...........................................................................................................................68
8.27.
S
WITCH
I
NTERRUPT
I
NDICATION
................................................................................................................................68
9.
CPU FUNCTION DESCRIPTION.................................................................................................................................68
9.1.
MIPS-4KE
C
...............................................................................................................................................................68
9.2.
SPI
F
LASH
..................................................................................................................................................................69
9.3.
SDRAM
I
NTERFACE
C
ONFIGURATION
(RTL8380M/RTL8382M
O
NLY
)..................................................................69
10.
INTERFACE DESCRIPTIONS......................................................................................................................................70
10.1.
QSGMII ....................................................................................................................................................................70
10.2.
RSGMII.....................................................................................................................................................................70
10.3.
SGMII .......................................................................................................................................................................71
10.4.
DDR1
SDRAM
(RTL8380M/RTL8382M
O
NLY
).....................................................................................................72
10.5.
DDR2
SDRAM
(RTL8380M/RTL8382M
O
NLY
).....................................................................................................73
10.6.
DDR3
SDRAM
(RTL8380M/RTL8382M
O
NLY
).....................................................................................................74
10.7.
SPI
F
LASH
I
NTERFACE
...............................................................................................................................................74
10.8.
UART........................................................................................................................................................................75
10.9.
EJTAG ......................................................................................................................................................................75
10.10.
I2C
M
ASTER FOR
EEPROM ......................................................................................................................................76
10.11.
I2C
S
LAVE
I
NTERFACE
...............................................................................................................................................76
10.12.
SPI
S
LAVE
I
NTERFACE
...............................................................................................................................................77
10.13.
S
ERIAL
LED...............................................................................................................................................................78
11.
ELECTRICAL AC/DC CHARACTERISTICS.............................................................................................................80
11.1.
A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................80
11.2.
O
PERATING
R
ANGE
....................................................................................................................................................80
11.3.
DC
C
HARACTERISTICS
...............................................................................................................................................81
11.4.
AC
C
HARACTERISTICS
...............................................................................................................................................81
11.4.1.
QSGMII Differential Transmitter Characteristics...........................................................................................81
11.4.2.
QSGMII Differential Receiver Characteristics................................................................................................82
11.4.3.
RSGMII Differential Transmitter Characteristics...........................................................................................84
11.4.4.
RSGMII Differential Receiver Characteristics................................................................................................85
11.4.5.
SGMII Differential Transmitter Characteristics..............................................................................................86
11.4.6.
SGMII Differential Receiver Characteristics ..................................................................................................87
11.4.7. DDR2 Characteristics .....................................................................................................................................88
11.4.8.
DDR
3
Characteristics .....................................................................................................................................89
11.4.9.
SPI Interface Characteristics...........................................................................................................................90
11.4.10.
SMI (MDC/MDIO) Interface Characteristics..................................................................................................91
12.
PACKAGE INFORMATION..........................................................................................................................................92
12.1.
LQFP216-E-PAD
(24*24
MM
)...................................................................................................................................92
13.
ORDERING INFORMATION........................................................................................................................................94
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