没有合适的资源?快使用搜索试试~ 我知道了~
首页UTMI+ Specification
UTMI+ Specification
![](https://csdnimg.cn/release/wenkucmsfe/public/img/star.98a08eaa.png)
The purpose of this document is to specify an interface to which USB 2.0 ASIC, ASSP, discrete PHY, system peripherals and IP vendors can develop USB2.0 products.
资源详情
资源推荐
![](https://csdnimg.cn/release/download_crawler_static/10745493/bg1.jpg)
UTMI+ Specification, Revision 1.0, February 25
th
, 2004
Page 1
UTMI+ Specification
Revision 1.0
![](https://csdnimg.cn/release/download_crawler_static/10745493/bg2.jpg)
UTMI+ Specification, Revision 1.0, February 25
th
, 2004
Page 2
Revision History
Revision Issue Date Comment
0.7 April 24
th
, 2002 Initial version
0.71 April 29
th
, 2002 Reworked the different levels
0.72 June 4
th
, 2002 Extended definition of OpMode
Added outline on how to implement multi-port host controllers using
UTMI+
0.8 June 17
th
, 2002 Promoted to version 0.8 to allow review by OTG workgroup members
0.81 July 3
rd
, 2002 Clarified Optional charge pump, rewording for grammer and clarity
0.82 July 22
nd
, 2002 Added signal IdPullup
Added signal FsSerialMode and legacy interface signals
Added signal TxBitstuffEnable / TxBitstuffEnableH
Removed signal SessEnd
0.83 October 23
rd
, 2002 Changed FsSerialMode into FsLsSerialMode
Added SessEnd signal back because there is still uncertainty that an
OTG system will work without this signal in all conditions.
Added clarifications
0.9rc January 8
th
, 2003 Added clarification of long EOP generation
Modified suspend/resume behaviour in host mode
Changed IdPullup timing
Added chapter on T&MT connector
0.9rc2 January 17
th
, 2003 Added section on ambiguities in UTMI v1.05 spec
Added clarification on HostDisconnect signal when PHY is in suspend
0.9rc3 February 7
th
, 2003 Changed TermSelect definition for LS devices
Changed clarification for RxActive/RxValid during transmit
Added clarification for LineState
0.9 February 21
st
, 2003 Added more clarification to LineState
Promoted to version 0.9 by OTG workgroup
0.91 October 13
th
, 2003 Changed time between IdPullup being asserted and IdDig having a valid
value.
Updated LineState tables
Changed behaviour of OpMode during chirp sequence
Updated disclaimer
0.92 November 13
th
, 2003 Changed time T1 during resume to be minimum 16 LS bit times. This
allows the transceiver to complete the resume signaling in a correct
way.
1.0 February 25
th
, 2004 Version approved by the Promoters and Adopters of UTMI+/ULPI
"The present Specification has been circulated for the sole benefit of legally-recognized Promoters, Adopters
and Contributors of the Specification. All rights are expressly reserved, including but not limited to intellectual
property rights under patents, trademarks, copyrights and trade secrets. The respective Promoter's, Adopter's
![](https://csdnimg.cn/release/download_crawler_static/10745493/bg3.jpg)
UTMI+ Specification, Revision 1.0, February 25
th
, 2004
Page 3
or Contributor's agreement entered into by Promoters, Adopters and Contributors sets forth their conditions of
use of the Specification."
Table of Contents
1. Introduction.................................................................................................................................6
1.1 Purpose..................................................................................................................................6
1.2 Audience................................................................................................................................6
1.3 Disclaimers.............................................................................................................................6
1.4 Relevant Documents................................................................................................................6
2. Definition of Different levels........................................................................................................7
2.1 UTMI+ level 0 : USB2.0 peripherals ...........................................................................................7
2.1.1 Additional requirements and clarifications on top of UTMI ................................................8
2.2 UTMI+ level 1 : USB2.0 peripherals, host controllers and On-the-Go devices (HS and FS only)......9
2.2.1 Additional signals for UTMI+ level 1. ..............................................................................9
2.2.2 Generation of long EOP ............................................................................................. 15
2.2.3 Data line pulsing........................................................................................................ 16
2.2.4 HS keep-alive generation............................................................................................ 16
2.2.5 UTMI+ level 1 transceiver core used in a USB2.0 peripheral........................................... 17
2.3 UTMI+ level 2 : USB2.0 peripherals, host controllers and On-the-Go devices (HS / FS / LS / no hub
support)...................................................................................................................................... 17
2.3.1 XcvrSelect(1:0) .......................................................................................................... 18
2.3.2 LS keep-alive generation ............................................................................................ 19
2.3.3 LineState.................................................................................................................. 19
2.4 UTMI+ level 3 : USB2.0 peripherals, host controllers and On-the-Go devices (HS / FS / LS / preamble)
20
2.4.1 XcvrSelect(1:0) .......................................................................................................... 20
2.4.2 Multi-port host controllers ........................................................................................... 21
3. Explanation of different signaling modes.................................................................................22
3.1 Chirp sequence..................................................................................................................... 22
3.2 Suspend / Resume signaling for downstream facing ports ......................................................... 22
3.3 Transmit error reporting for downstream facing ports ................................................................. 24
3.4 Selection of different signaling modes for upstream and downstream facing ports ........................ 25
4. T&MT Connector .......................................................................................................................26
Figures
Figure 1 : UTMI+ levels ...........................................................................................................................7
Figure 2 : UTMI+ level 0 entity diagram (16-bit interface).............................................................................8
Figure 3 : UTMI+ level 1 entity diagram...................................................................................................10
Figure 4 : HostDisconnect behaviour (signals are not on scale).................................................................14
Figure 5 : Data line pulsing for a Dual-Role B-device ................................................................................16
Figure 6 : HS keep-alive generation ........................................................................................................16
Figure 7 : UTMI+ level 2 entity diagram...................................................................................................18
Figure 8 : LS keep-alive generation.........................................................................................................19
![](https://csdnimg.cn/release/download_crawler_static/10745493/bg4.jpg)
UTMI+ Specification, Revision 1.0, February 25
th
, 2004
Page 4
Figure 9 : Reset sequence for a HS peripheral connected to a HS Host Controller ......................................22
Figure 10 : Resume signaling on downstream facing ports........................................................................23
Figure 11 : Transmit error reporting for downstream facing ports................................................................24
Tables
Table 1 : Filtering of LineState .................................................................................................................9
Table 2 : UTMI+ level 1 transceiver core used in a USB2.0 peripheral ........................................................17
Table 3 : LineState for upstream facing ports (DpPulldown and DmPulldown = 0)........................................20
Table 4 : LineState for downstream facing ports(DpPulldown and DmPulldown = 1).....................................20
Table 5 : Different signaling modes for upstream and downstream facing ports ...........................................25
Table 6 : T&MT connector pinning
[1]
........................................................................................................26
![](https://csdnimg.cn/release/download_crawler_static/10745493/bg5.jpg)
UTMI+ Specification, Revision 1.0, February 25
th
, 2004
Page 5
Acronyms and Terms
FS Full-Speed
HS High-Speed
IC Integrated Circuit
LS Low-Speed
OTG On-The-Go
SE0 Single Ended Zero
USB Universal Serial Bus
USB-IF USB Implementers Forum
UTMI USB 2.0 Transceiver Macrocell Interface
Contributors
Bart Vertenten Philips
Srinivas Pattamatta Philips
Jerome Tjia Philips
Chung Wing Yan Philips
Farran Mackay Philips
Chris Kolb ARC
Christopher Meyers ARC
David Cobbs Cypress
David Wooten Cypress
Eric Huang Synopsys
Ravikumar Govindaraman Synopsys
Saleem Mohammad Synopsys
Michael Pennell SMSC
Nabil Takla Innovative
Paul Berg MCCI
Peter Hirt ST Microelectronics
Alok Kaushik ST Microelectronics
Rob Douglas Mentor Graphics
Andy King Mentor Graphics
Zong Liang Wu TransDimension
Hemal Doshi Portalplayer Inc
剩余25页未读,继续阅读
![pdf](https://img-home.csdnimg.cn/images/20210720083512.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![pdf](https://img-home.csdnimg.cn/images/20210720083512.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![application/msword](https://img-home.csdnimg.cn/images/20210720083327.png)
![pdf](https://img-home.csdnimg.cn/images/20210720083512.png)
![](https://profile-avatar.csdnimg.cn/default.jpg!1)
caicaixuehua
- 粉丝: 0
- 资源: 15
上传资源 快速赚钱
我的内容管理 收起
我的资源 快来上传第一个资源
我的收益
登录查看自己的收益我的积分 登录查看自己的积分
我的C币 登录后查看C币余额
我的收藏
我的下载
下载帮助
![](https://csdnimg.cn/release/wenkucmsfe/public/img/voice.245cc511.png)
会员权益专享
最新资源
- VMP技术解析:Handle块优化与壳模板初始化
- C++ Primer 第四版更新:现代编程风格与标准库
- 计算机系统基础实验:缓冲区溢出攻击(Lab3)
- 中国结算网上业务平台:证券登记操作详解与常见问题
- FPGA驱动的五子棋博弈系统:加速与创新娱乐体验
- 多旋翼飞行器定点位置控制器设计实验
- 基于流量预测与潮汐效应的动态载频优化策略
- SQL练习:查询分析与高级操作
- 海底数据中心散热优化:从MATLAB到动态模拟
- 移动应用作业:MyDiaryBook - Google Material Design 日记APP
- Linux提权技术详解:从内核漏洞到Sudo配置错误
- 93分钟快速入门 LaTeX:从入门到实践
- 5G测试新挑战与罗德与施瓦茨解决方案
- EAS系统性能优化与故障诊断指南
- Java并发编程:JUC核心概念解析与应用
- 数据结构实验报告:基于不同存储结构的线性表和树实现
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
![](https://img-home.csdnimg.cn/images/20220527035711.png)
![](https://img-home.csdnimg.cn/images/20220527035711.png)
![](https://img-home.csdnimg.cn/images/20220527035111.png)
安全验证
文档复制为VIP权益,开通VIP直接复制
![](https://csdnimg.cn/release/wenkucmsfe/public/img/green-success.6a4acb44.png)