没有合适的资源?快使用搜索试试~ 我知道了~
首页veriloga的模型导入hspice的方法
资源详情
资源评论
资源推荐
HSPICE
®
Simulation and Analysis User Guide 429
X-2005.09
12
12Using HSPICE with Verilog-A
Describes how to use Verilog-A in HSPICE simulations.
Verilog-A is used to create and use analog behavioral descriptions that
encapsulate high-level behavioral and structural descriptions of systems and
components.
The language allows the behavior of each model, or module, to be described
mathematically in terms of its ports and parameters applied to an instance of
the module. A module can be defined at a level of abstraction appropriate for
the model and analysis, including architectural design, and verification. Verilog-
A supports both a top-down design as well as a bottom-up verification
methodology.
Verilog-A was derived from the IEEE 1364 Verilog Hardware Description
Language (HDL) specification and is intended for describing behavior in analog
systems. The Verilog-A language that HSPICE supports is compliant to Verilog-
AMS LRM2.1 from Accellera with some LRM2.2 features added, such as
$table_model, $param_given, output parameters, and the above function.
The Verilog-A implementation in HSPICE supports a mixed design of Verilog-A
descriptions and transistor-level SPICE netlists with a simple use model. Most
analysis features available in HSPICE are supported for Verilog-A based
devices, including AC, DC, transient analysis, statistical analysis, and
optimization.
430 HSPICE
®
Simulation and Analysis User Guide
X-2005.09
12: Using HSPICE with Verilog-A
Getting Started
Getting Started
This section explains how to get started using a compact device model written
in Verilog-A in HSPICE.
Verilog-A devices use the following conventions:
■
modules are loaded into the simulator with either the .hdl netlist command
or the –hdl HSPICE command-line option.
■
modules are instantiated in the same manner as HSPICE sub-circuits. The
first character for the name of instance should be “X”.
■
instance and model parameters can be modified in the same way as other
HSPICE instances.
■
module names should not conflict with any HSPICE built-in device keyword
(for example, C, D, NMOS, PMOS, and so on). If this happens, HSPICE
issues a warning message and ignores the Verilog-A module definition.
■
node voltages and branch currents can be output using conventional output
commands.
Note: Before you run a circuit with a Verilog-A module, check to be sure that
your environment has been set up to source the cshrc.meta file. For details,
see the HSPICE chapter to the Installation Guide.
The following example illustrates how a compact device model written in
Verilog-A can be analyzed with HSPICE.
Example: JFET Compact Device Model
HSPICE contains a large number of compact device models coded natively in
the simulator. Verilog-A provides a convenient method to introduce new
compact models. The JFET device model uses a simple expression to relate
the source-drain current to the gate voltage.
The simplified Verilog-A description of this model is shown in below.
`include "constants.vams"
`include "disciplines.vams"
module jfet(d, g, s);
parameter real Vto = -2.0 from (-inf:inf); // Threshold voltage
parameter real Beta = 1.0e-4 from [0:inf);// Transconductance
parameter real Lambda = 0.0 from [0:inf); // Channel modulation
electrical d, g, s;
HSPICE
®
Simulation and Analysis User Guide 431
X-2005.09
12: Using HSPICE with Verilog-A
Getting Started
real Id, Vgs, Vds;
analog begin
Vgs = V(g,s);
Vds = V(d,s);
if (Vds <= Vgs-Vto)
Id = Beta*(1+Lambda*Vds)*Vds*(2*(Vgs-Vto)- Vds);
else if (Vgs-Vto < Vds)
Id = Beta*(1+Lambda*Vds)*(Vgs-Vto)*(Vgs-Vto);
I(d,s) <+ Id;
end
endmodule
In this example the module name is jfet and the module has three ports, named
d, g, and s. Three parameters, Vto, Beta, and Lambda, can be passed in from
the netlist. The electrical behavior is defined between the analog begin and end
statements. The node voltages across the gate to source and drain to source is
accessed and assigned to the variables Vgs and Vgd. These values are used
to determine the drain-source current, Id. The calculated current is contributed
to the branch from d to s in the final statement using the contribution operator,
<+.
This Verilog-A module is loaded into HSPICE with an .HDL command in the
netlist. The device is then instantiated using the X prefix for the device name.
The connectivity, module name, and parameter assignments follow the format
of a sub-circuit device. The following instantiation line in the netlist is for this
device:
x1 drain gate source jfet Beta=1.1e-4 lambda=0.01
The nodes drain, gate, and source are mapped to the ports d, g, s in the same
order as defined in the module definition. Any parameters in the instantiation
line are passed to the module; otherwise, the default value defined on the
parameter declaration line is used. The parameter declaration allows ranges
and exclusions to be easily defined.
The parameter passed in from the netlist is tested during the simulation and a
run- time error occurs if the parameter is out of the allowed range.
The device is used in the HSPICE netlist in exactly the same manner that a
built-in device is used. The netlist example shown in below performs a simple
DC-IV analysis.
Verilog-A version of the SPICE JFET
.hdl jfet.va
.options post=1
VCC Drain 0 3.0
432 HSPICE
®
Simulation and Analysis User Guide
X-2005.09
12: Using HSPICE with Verilog-A
Getting Started
VG Gate 0 0.5
VS Source 0 0.0
X1 Drain Gate Source jfet Vto=-2.0 Beta=1.1e-4 Lambda=0.01
.dc VCC 0.0 4.0 0.01 VG -2.0 0.0 0.5
.print I(VCC)
.end
When the simulation is performed, the program compiles the Verilog-A source
file into a compiled object file. This object file is automatically cached and
subsequent simulations do not require the compile step unless the Verilog-A
source file is modified. After simulation, HSPICE outputs the data in the same
fashion as other devices. In this example the drain-source current is plotted as
a function of Vds and parameterized by Vgs. Figure 73 displays the plot of the
drain-source current for this model.
Figure 73 IV Characteristics of a Verilog-A JFET
HSPICE
®
Simulation and Analysis User Guide 433
X-2005.09
12: Using HSPICE with Verilog-A
Introduction to Verilog-A
Introduction to Verilog-A
The following is a Verilog-A module example provides an overview of the
language. See the Verilog-AMS LRM2.1 from Accellera for syntax and usage
details.
Verilog-A Module Template
The following basic template illustrates basic of the language's features.
`include "disciplines.vams" // Natures and disciplines
`include "constants.vams" // Common physical and math
// constants
module my_model(port1, bus);
electrical port1;
electrical [0:1] bus;
parameter real real_param = 1.0 from [0:inf);
parameter integer int_param = 1 from [-1:1] exclude 0;
real real_var;
analog begin
@ ( initial_step ) begin
/* Code inside an initial_step block is executed
at the first step of each analysis */
end
real_var = I(port1); // Current port1 to ground
V(bus[0], bus[1]) <+ real_var * real_param * int_param;
@ ( final_step ) begin
/* Code inside an final_step block is executed
at the last step of each analysis */
end
end
endmodule
剩余39页未读,继续阅读
jokeking1994
- 粉丝: 2
- 资源: 5
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- RTL8188FU-Linux-v5.7.4.2-36687.20200602.tar(20765).gz
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
- SPC统计过程控制程序.pptx
- SPC统计方法基础知识.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论2