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IEEE Std 1364™-2005

(Revision of IEEE Std 1364-2001)

IEEE Standard for Verilog

Hardware Description Language

I E E E

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New York, NY 10016-5997, USA

7 April 2006

IEEE Computer Society

Sponsored by the

Design Automation Standards Committee

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Introduction

The Verilog hardware description language (HDL) became an IEEE standard in 1995 as IEEE Std 1364-

1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard

textual format for a variety of design tools, including verification simulation, timing analysis, test analysis,

and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice

by an overwhelming number of integrated circuit (IC) designers.

Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,

and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is

essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in

which expressions of both variables and nets can continuously drive values onto nets, provide the basic

structural construct. Procedural assignments, in which the results of calculations involving variable and net

values can be stored into variables, provide the basic behavioral construct. A design consists of a set of mod-

ules, each of which has an input/output (I/O) interface, and a description of its function, which can be struc-

tural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets.

The Verilog language is extensible via the programming language interface (PLI) and the Verilog proce-

dural interface (VPI) routines. The PLI/VPI is a collection of routines that allows foreign functions to access

information contained in a Verilog HDL description of the design and facilitates dynamic interaction with

simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation

and computer-assisted design (CAD) systems, customized debugging tasks, delay calculators, and

annotators.

The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel Univer-

sity in England under a contract to produce a test generation system for the British Ministry of Defense.

HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification

simulation, timing analysis, fault simulation, and test generation.

In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent

Open Verilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board of

Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993, the first IEEE

working group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard as

IEEE Std 1364-1995.

After the standardization process was complete, the IEEE P1364 Working Group started looking for feed-

back from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. This

led to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001.

With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identify

outstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-

ing on standardizing SystemVerilog in 2001, additional issues were identified that could possibly have led to

incompatibilities between Verilog 1364 and SystemVerilog. The IEEE P1364 Working Group was estab-

lished as a subcomittee of the SystemVerilog P1800 Working Group to help ensure consistent resolution of

such issues. The result of this collaborative work is this standard, IEEE Std 1364-2005.

This introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog

Hardware Description Language.

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