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Proposed VESA DisplayPort Standard Ver.1.1a Draft 6
©Copyright 2007 Video Electronics Standards Association Page 1 of 243
Proposed DisplayPort™ Standard
860 Hillview Court, Suite 150 Phone: 408 957 9270
Milpitas, CA 95035 Fax: 408 957 9277
URL: www.vesa.org
Proposed DisplayPort Standard
Version 1 Revision 1a
(Version 1 Revision 1 with Errata Correction/Clarification)
Draft 6
December 10, 2007
Purpose
The purpose of this document is to define a flexible system and apparatus capable of transporting video, audio
and other data between a Source Device and a Sink Device over a digital communications interface.
Summary
The DisplayPort™ standard specifies an open digital communications interface for use in both internal
connections, such as interfaces within a PC or monitor, and external display connections, including interfaces
between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and
TV display. This DisplayPort Ver.1.1a document incorporates all the errata correction and clarification items
on DisplayPort Ver.1.1 as described in Errata Corrections and Clarifications on DisplayPort Standard Version
1. Revision 1.
Proposed VESA DisplayPort Standard Ver.1.1a Draft 6
©Copyright 2007 Video Electronics Standards Association Page 2 of 243
Table of Contents
ACKNOWLEDGEMENTS ............................................................................................................................10
REVISION HISTORY ....................................................................................................................................13
1 INTRODUCTION ....................................................................................................................................14
1.1 DISPLAYPORT SPECIFICATION ORGANIZATION......................................................................................14
1.2 DISPLAYPORT OBJECTIVES ...................................................................................................................14
1.2.1 Key Industry Needs for DisplayPort ............................................................................................15
1.2.2 DisplayPort Technical Objectives................................................................................................15
1.2.3 DisplayPort External Connection Objectives ..............................................................................16
1.2.4 DisplayPort Internal Connection Objectives ...............................................................................17
1.2.5 DisplayPort CE Connection Objectives.......................................................................................17
1.2.6 Content Protection for DisplayPort.............................................................................................17
1.3 ACRONYMS............................................................................................................................................17
1.4 GLOSSARY.............................................................................................................................................20
1.5 REFERENCES.........................................................................................................................................24
1.6 NOMENCLATURE FOR BIT AND BYTE ORDERING....................................................................................25
1.6.1 Bit Ordering .................................................................................................................................25
1.6.2 Byte Ordering...............................................................................................................................25
1.7 OVERVIEW OF DISPLAYPORT.................................................................................................................27
1.7.1 Make-up of the Main Link............................................................................................................27
1.7.2 Make-up of AUX CH ....................................................................................................................28
1.7.3 Link Configuration and Management ..........................................................................................29
1.7.4 Layered, Modular Architecture....................................................................................................29
2 LINK LAYER ...........................................................................................................................................31
2.1 INTRODUCTION ....................................................................................................................................31
2.1.1 Number of Lanes and Per-lane Data Rate...................................................................................32
2.1.2 Number of Main, Uncompressed Video Streams..........................................................................32
2.1.3 Basic Functions............................................................................................................................32
2.1.4 DisplayPort Device Types and Link Topology.............................................................................32
2.2 ISOCHRONOUS TRANSPORT SERVICES.................................................................................................36
2.2.1 Main Stream to Main Link Lane Mapping in the Source Device.................................................36
2.2.2 Stream Reconstruction in the Sink ...............................................................................................60
2.2.3 Stream Clock Recovery ................................................................................................................62
2.2.4 Main Stream Attribute Data Transport........................................................................................64
2.2.5 Secondary-data Packing Formats................................................................................................68
2.2.6 ECC for Secondary-data Packet ..................................................................................................81
2.3 AUX CH STATES AND ARBITRATION .................................................................................................87
2.3.1 AUX CH STATES Overview.........................................................................................................87
2.3.2 Link Layer Arbitration Control....................................................................................................91
2.3.3 Policy Maker AUX CH Management...........................................................................................91
2.3.4 Detailed Source AUX CH State Description................................................................................91
2.3.5 Detailed Sink AUX CH State Description....................................................................................92
2.4 AUX CH SYNTAX ...............................................................................................................................94
2.4.1 Command definition.....................................................................................................................95
2.4.2 AUX CH Response / Reply Time-outs ..........................................................................................97
2.4.3 Native AUX CH Request Transaction Syntax ..............................................................................97
2.4.4 Native AUX CH Reply Transaction Syntax..................................................................................97
2.4.5 I
2
C bus transaction mapping onto AUX CH Syntax.....................................................................98
2.4.6 Conversion of I
2
C Transaction to Native AUX CH Transaction (INFORMATIVE) ..................116
Proposed VESA DisplayPort Standard Ver.1.1a Draft 6
©Copyright 2007 Video Electronics Standards Association Page 3 of 243
2.5 AUX CH SERVICES ...........................................................................................................................117
2.5.1 Stream Transport Initiation Sequence........................................................................................118
2.5.2 Stream Transport Termination Sequence...................................................................................119
2.5.3 AUX CH Link Services...............................................................................................................119
2.5.4 AUX CH Device Services...........................................................................................................143
3 PHYSICAL LAYER...............................................................................................................................145
3.1 INTRODUCTION ..................................................................................................................................145
3.1.1 PHY Functions ...........................................................................................................................145
3.1.2 Link Layer-PHY Interface Signals .............................................................................................146
3.1.3 PHY-Media Interface Signals.....................................................................................................147
3.2 DP_PWR FOR BOX-TO-BOX DISPLAYPORT CONNECTION ...............................................................148
3.2.1 DP_PWR User Detection Method..............................................................................................149
3.2.2 DP_PWR Wire ...........................................................................................................................149
3.2.3 Inrush Current............................................................................................................................149
3.2.4 Voltage Droop............................................................................................................................149
3.2.5 Over Current Protection (OCP).................................................................................................149
3.3 HOT PLUG / UNPLUG DETECT CIRCUITRY.........................................................................................150
3.4 AUX CHANNEL .................................................................................................................................151
3.4.1 AUX Channel Logical Sub-Block...............................................................................................151
3.4.2 AUX Channel Electrical Sub-Block ...........................................................................................153
3.5 MAIN LINK.........................................................................................................................................158
3.5.1 Main Link Logic Sub-block ........................................................................................................158
3.5.2 Main Link Electrical Sub-Block.................................................................................................167
3.5.3 Transmitter and Receiver Electrical Specifications...................................................................168
3.5.4 ESD and EOS Protection ...........................................................................................................183
4 MECHANICAL ......................................................................................................................................184
4.1 CABLE-CONNECTOR ASSEMBLY SPECIFICATIONS (FOR BOX-TO-BOX).............................................184
4.1.1 Cable-Connector Assembly Definition.......................................................................................185
4.1.2 Type of Bulk Cable.....................................................................................................................186
4.1.3 Impedance Profile......................................................................................................................187
4.1.4 Insertion Loss & Return Loss.....................................................................................................187
4.1.5 High-bit-rate Cable-Connector Assembly Specification............................................................188
4.1.6 Reuced Bit Rate Cable-Connector Assembly Specification .......................................................195
4.2 CONNECTOR SPECIFICATION .............................................................................................................199
4.2.1 External connector.....................................................................................................................199
4.2.2 Panel-side Internal Connector (INFORMATIVE) .....................................................................211
5 SOURCE / SINK DEVICE INTEROPERABILITY...........................................................................222
5.1 SOURCE DEVICE ................................................................................................................................222
5.1.1 Stream Source Requirement.......................................................................................................222
5.1.2 Source Device Link Configuration Requirement........................................................................224
5.1.3 Source Device Behavior on Stream Timing Change..................................................................225
5.1.4 Source Device Behavior upon HPD Pulse Detection ................................................................226
5.1.5 Sink Device Power Management by a Source Device................................................................227
5.2 SINK DEVICE......................................................................................................................................228
5.2.1 Stream Sink Requirement ...........................................................................................................228
5.2.2 Sink Device Link Configuration Requirement............................................................................228
5.2.3 Sink Device Behavior on Stream Timing Change ......................................................................229
5.2.4 Toggling of HPD Signal for Status Change Notification...........................................................230
5.2.5 Sink Device Power-Save Mode ..................................................................................................230
5.3 BRANCH DEVICE................................................................................................................................231
Proposed VESA DisplayPort Standard Ver.1.1a Draft 6
©Copyright 2007 Video Electronics Standards Association Page 4 of 243
5.3.1 EDID Access Handling Requirement.........................................................................................231
5.3.2 Branch Device Link Configuration Requirements .....................................................................231
5.4 CABLE-CONNECTOR ASSEMBLY .......................................................................................................235
5.4.1 Box-to-Box, End-User-Detachable Cable Assembly..................................................................235
5.4.2 Embedded and Captive Cable Assembly....................................................................................235
6 APPENDIX A: LINK LAYER EXTENSION FOR DPCP SUPPORT .............................................236
6.1 DPCP BULK ENCRYPTION/DECRYPTION BLOCKS ............................................................................236
6.2 AUX CH TRANSACTIONS FOR DPCP ................................................................................................236
7 APPENDIX B: AUDIO TRANSPORT (INFORMATIVE).................................................................237
7.1 AUDIO STREAM COMPONENTS ...........................................................................................................237
7.2 ASSOCIATION OF THREE PACKET TYPES VIA PACKET ID .................................................................237
7.3 SCHEDULING OF AUDIO STREAM PACKET TRANSMISSION ...............................................................237
7.3.1 Handling of an Audio Format Change.......................................................................................238
7.4 STRUCTURE OF AUDIO STREAM PACKET ..........................................................................................239
7.4.1 One or Two Channel Audio........................................................................................................239
7.4.2 Three to Eight Channel Audio....................................................................................................239
7.5 CHANNEL-TO-SPEAKER MAPPING .....................................................................................................240
7.6 TRANSFER OF SAMPLE FREQUENCY INFORMATION ..........................................................................241
8 APPENDIX C: SINK EVENT NOTIFICATION EXAMPLE (INFORMATIVE) ..........................242
8.1 MUTUAL IDENTIFICATION BY SOURCE AND SINK .............................................................................242
8.2 IRQ_HPD PULSE AND SINK-SPECIFIC IRQ.......................................................................................242
9 APPENDIX D: SUMMARY OF FEATURES RELATED TO POWER MANAGEMENT
(INFORMATIVE)..........................................................................................................................................243
9.1 AUX CH REQUEST TRANSACTION READINESS BY SINK DEVICE .....................................................243
9.2 SOURCE DETECTION ..........................................................................................................................243
9.3 LINK TRAINING WITHOUT AUX CH HANDSHAKE (FAST LINK TRAINING) ......................................243
List of Tables
TABLE 0-1: MAIN CONTRIBUTORS ......................................................................................................................................10
TABLE 1-1: LIST OF ACRONYMS ..........................................................................................................................................17
TABLE 1-2: GLOSSARY OF TERMS........................................................................................................................................20
TABLE 1-3: REFERENCE DOCUMENTS .................................................................................................................................24
TABLE 2-1: CONTROL SYMBOLS FOR FRAMING...................................................................................................................40
TABLE 2-2: PIXEL STEERING INTO MAIN LINK LANES.........................................................................................................40
TABLE 2-3: VB-ID BIT DEFINITION ....................................................................................................................................42
TABLE 2-4: 30 BPP RGB (10 BITS / COMPONENT) 1366 X 768 PACKING TO A FOUR LANE MAIN LINK ...............................45
TABLE 2-5: 24 BPP RGB TO A FOUR LANE MAIN LINK MAPPING........................................................................................46
TABLE 2-6: 24 BPP RGB MAPPING TO A TWO LANE MAIN LINK .........................................................................................46
TABLE 2-7: 24 BPP RGB MAPPING TO A ONE LANE MAIN LINK..........................................................................................46
TABLE 2-8: 18 BPP RGB MAPPING TO A FOUR LANE MAIN LINK........................................................................................47
TABLE 2-9: 18 BPP RGB MAPPING TO A TWO LANE MAIN LINK .........................................................................................47
TABLE 2-10: 18 BPP RGB MAPPING TO A ONE LANE MAIN LINK........................................................................................47
TABLE 2-11: 30 BPP RGB MAPPING TO A FOUR LANE MAIN LINK......................................................................................48
TABLE 2-12: 30 BPP RGB MAPPING TO A TWO LANE MAIN LINK .......................................................................................48
TABLE 2-13: 30 BPP RGB MAPPING TO A ONE LANE MAIN LINK........................................................................................49
TABLE 2-14: 36 BPP RGB MAPPING TO A FOUR LANE MAIN LINK ......................................................................................50
TABLE 2-15: 36 BPP RGB MAPPING TO A TWO LANE MAIN LINK .......................................................................................50
TABLE 2-16: 36 BPP RGB MAPPING TO A ONE LANE MAIN LINK........................................................................................50
TABLE 2-17: 48 BPP RGB MAPPING TO A FOUR LANE MAIN LINK......................................................................................51
TABLE 2-18: 48 BPP RGB MAPPING TO A TWO LANE MAIN LINK .......................................................................................51
TABLE 2-19: 48 BPP RGB MAPPING TO A ONE LANE MAIN LINK........................................................................................51
TABLE 2-20: 16 BPP YCBCR
4:2:2 MAPPING TO A FOUR LANE MAIN LINK ........................................................................52
Proposed VESA DisplayPort Standard Ver.1.1a Draft 6
©Copyright 2007 Video Electronics Standards Association Page 5 of 243
T
ABLE 2-21: 16 BPP YCBCR
4:2:2 MAPPING TO A TWO LANE MAIN LINK..........................................................................52
TABLE 2-22: 16 BPP YCBCR
4:2:2 MAPPING TO A ONE LANE MAIN LINK ..........................................................................52
TABLE 2-23: 20 BPP YCBCR
4:2:2 MAPPING TO A FOUR LANE MAIN LINK ........................................................................53
TABLE 2-24: 20 BPP YCBCR
4:2:2 MAPPING TO A TWO LANE MAIN LINK..........................................................................53
TABLE 2-25: 20 BPP YCBCR
4:2:2 MAPPING TO A ONE LANE MAIN LINK .........................................................................53
TABLE 2-26: 24 BPP YCBCR
4:2:2 MAPPING TO A FOUR LANE MAIN LINK ........................................................................54
TABLE 2-27: 24 BPP YCBCR
4:2:2 MAPPING TO A TWO LANE MAIN LINK .........................................................................54
TABLE 2-28: 24 BPP YCBCR
4:2:2 MAPPING TO A ONE LANE MAIN LINK..........................................................................54
TABLE 2-29: 32 BPP YCBCR
4:2:2 MAPPING TO A FOUR LANE MAIN LINK.........................................................................55
TABLE 2-30: 32 BPP YCBCR
4:2:2 MAPPING TO A TWO LANE MAIN LINK .........................................................................55
TABLE 2-31: 32 BPP YCBCR
4:2:2 MAPPING TO A ONE LANE MAIN LINK..........................................................................55
TABLE 2-32: TRANSFER UNIT OF 30 BPP RGB VIDEO OVER A 2.7 GBPS PER LANE MAIN LINK..........................................58
TABLE 2-33: SECONDARY-DATA PACKET HEADER .............................................................................................................68
TABLE 2-34: SECONDARY-DATA PACKET TYPE ..................................................................................................................68
TABLE 2-35: HEADER BYTES OF INFOFRAME PACKET ........................................................................................................70
TABLE 2-36: HEADER BYTES OF AUDIO_TIMESTAMP PACKET ...........................................................................................72
TABLE 2-37: EXAMPLES OF MAUD AND NAUD VALUES ......................................................................................................72
TABLE 2-38: HEADER BYTES OF AUDIO_STREAM PACKET .................................................................................................73
TABLE 2-39: AUDIO_STREAM PACKET OVER THE MAIN LINK FOR ONE OR TWO CHANNEL AUDIO....................................75
TABLE 2-40: AUDIO STREAM PACKET OVER THE MAIN LINK FOR THREE TO EIGHT CHANNEL AUDIO ...............................75
TABLE 2-41: BIT DEFINITION OF THE PAYLOAD OF AN AUDIO_STREAM PACKET WITH IEC60958-LIKE CODING ...............77
TABLE 2-42: HEADER BYTES OF AN EXTENSION PACKET....................................................................................................80
TABLE 2-43: SOURCE AUX CH STATE AND EVENT DESCRIPTIONS ....................................................................................91
TABLE 2-44: SINK AUX CH STATE AND EVENT DESCRIPTION ...........................................................................................92
TABLE 2-45: BIT / BYTE SIZE OF VARIOUS DATA TYPES OF AUX CH SYNTAX ..................................................................94
TABLE 2-46: I
2
C WRITE TRANSACTION EXAMPLE 1..........................................................................................................100
TABLE 2-47: I
2
C WRITE TRANSACTION METHOD 1 WITH A SLOW I
2
C BUS IN THE SINK DEVICE ......................................103
TABLE 2-48: I
2
C WRITE TRANSACTION METHOD 2...........................................................................................................107
TABLE 2-49: I
2
C READ TRANSACTION METHOD 1.............................................................................................................109
TABLE 2-50: I
2
C READ TRANSACTION EXAMPLE 2 ...........................................................................................................111
TABLE 2-51: I
2
C WRITE FOLLOWED BY AN I
2
C READ .......................................................................................................114
TABLE 2-52: ADDRESS MAPPING FOR THE DPCD (DISPLAYPORT CONFIGURATION DATA)..............................................121
TABLE 2-53: ANSI8B/10B ENCODING AND SCRAMBLING RULES FOR LINK MANAGEMENT ............................................141
TABLE 2-54: DISPLAYPORT ADDRESS MAPPING FOR DEVICE SERVICES ...........................................................................143
TABLE 3-1: DP_PWR SPECIFICATION FOR BOX-TO-BOX DISPLAYPORT CONNECTION.....................................................148
TABLE 3-2: HOT PLUG DETECT SIGNAL SPECIFICATION....................................................................................................150
TABLE 3-3: DISPLAYPORT AUX CHANNEL ELECTRICAL SPECIFICATIONS........................................................................153
TABLE 3-4: MASK VERTICES FOR AUX CH AT TRANSMITTING IC PACKAGES PINS (INFORMATIVE)................................155
TABLE 3-5: MASK VERTICES FOR AUX CH AT CONNECTOR PINS OF TRANSMITTING DEVICE (NORMATIVE) ..................155
TABLE 3-6: MASK VERTICES FOR AUX CH AT CONNECTOR PINS OF RECEIVING DEVICE (NORMATIVE).......................156
TABLE 3-7: MASK VERTICES FOR AUX CH AT RECEIVING IC PACKAGES PINS (INFORMATIVE) ......................................157
TABLE 3-8: ANSI 8B/10B SPECIAL CHARACTERS FOR DISPLAYPORT CONTROL SYMBOLS..............................................160
TABLE 3-9: SYMBOL PATTERNS OF LINK TRAINING ..........................................................................................................161
TABLE 3-10: DISPLAYPORT MAIN LINK TRANSMITTER (MAIN TX) SPECIFICATIONS .......................................................168
TABLE 3-11: DISPLAYPORT MAIN LINK RECEIVER (MAIN RX) SPECIFICATIONS..............................................................170
TABLE 3-12: ALLOWED VDIFF_PP - PRE-EMPHASIS COMBINATIONS .................................................................................172
TABLE 3-13: DIFFERENTIAL NOISE BUDGET .....................................................................................................................177
TABLE 3-14: MASK VERTICES FOR HIGH BIT RATE...........................................................................................................180
TABLE 3-15: MASK VERTICES FOR REDUCED BIT RATE....................................................................................................180
TABLE 3-16: SINK EYE VERTICES FOR TP3 AT HIGH BIT RATE........................................................................................181
TABLE 3-17: SINK EYE VERTICES AT TP3 FOR REDUCED BIT RATE.................................................................................182
TABLE 3-18: TP3 EYE MASK VERTICES AT HIGH BIT RATE FOR EMBEDDED CONNECTION (INFORMATIVE)..............182
TABLE 3-19: TP3 EYE MASK VERTICES FOR REDUCED BIT RATE FOR EMBEDDED CONNECTION (INFORMATIVE) .....182
TABLE 4-1: IMPEDANCE PROFILE VALUES FOR CABLE ASSEMBLY ...................................................................................187
TABLE 4-2: MIXED MODE DIFFERENTIAL / COMMON RELATIONS OF S-PARAMETERS.......................................................188
TABLE 4-3: SOURCE-SIDE CONNECTOR PIN ASSIGNMENT.................................................................................................199
TABLE 4-4: SINK-SIDE CONNECTOR PIN ASSIGNMENT......................................................................................................199
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