GD32F4xx User Manual
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2.3.10. Sector erase/program protection .................................................................................................... 65
2.3.11. D-bus read protection ....................................................................................................................... 66
2.3.12. Security protection ............................................................................................................................ 66
2.4. FMC registers ..................................................................................................................... 67
2.4.1. Wait state register (FMC_WS) ........................................................................................................ 67
2.4.2. Unlock key register (FMC_KEY)..................................................................................................... 67
2.4.3. Option byte unlock key register (FMC_OBKEY) .......................................................................... 68
2.4.4. Status register (FMC_STAT) ........................................................................................................... 68
2.4.5. Control register (FMC_CTL) ............................................................................................................ 69
2.4.6. Option byte control register 0 (FMC_OBCTL0) ............................................................................ 71
2.4.7. Option byte control register 1 (FMC_OBCTL1) ............................................................................ 73
2.4.8. Wait state enable register (FMC_WSEN) ..................................................................................... 73
2.4.9. Product ID register (FMC_PID) ...................................................................................................... 74
3. Power management unit (PMU) ............................................................................... 75
3.1. Introduction ....................................................................................................................... 75
3.2. Main features .................................................................................................................... 75
3.3. Function description........................................................................................................... 75
3.3.1. Battery backup domain .................................................................................................................... 76
3.3.2. Backup SRAM ................................................................................................................................... 77
3.3.3. VDD/VDDA power domain .............................................................................................................. 77
3.3.4. 1.2V power domain ........................................................................................................................... 80
3.3.5. Power saving modes ........................................................................................................................ 81
3.4. PMU registers .................................................................................................................... 83
3.4.1. Control register (PMU_CTL) ........................................................................................................... 83
3.4.2. Control and status register (PMU_CS) .......................................................................................... 85
4. Reset and clock unit (RCU) ...................................................................................... 88
4.1. Reset control unit (RCTL) .................................................................................................... 88
4.1.1. Overview ............................................................................................................................................ 88
4.1.2. Function overview ............................................................................................................................. 88
4.2. Clock control unit (CCTL) ............................................................................................. 89
4.2.1. Overview ............................................................................................................................................ 89
4.2.2. Characteristics................................................................................................................................... 91
4.2.3. Function overview ............................................................................................................................. 92
4.3. Register definition.......................................................................................................... 96
4.3.1. Control register (RCU_CTL) ............................................................................................................ 96
4.3.2. PLL register (RCU_PLL) .................................................................................................................. 98
4.3.3. Clock configuration register 0 (RCU_CFG0) .............................................................................. 100
4.3.4. Clock interrupt register (RCU_INT) .............................................................................................. 102
4.3.5. AHB1 reset register (RCU_AHB1RST) ....................................................................................... 105
4.3.6. AHB2 reset register (RCU_AHB2RST) ....................................................................................... 108
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