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首页TMS320F28035的ePWM设置详细手册
TMS320F28035的ePWM设置详细手册
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更新于2023-03-16
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本文档主要针对于TI DSP TMS320F2000系列的,它里面有关于ePWM模块的具体寄存器设置,可以当做手册来用。
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TMS320x2802x, 2803x Piccolo Enhanced Pulse
Width Modulator (ePWM) Module
Reference Guide
Literature Number: SPRUGE9E
December 2008–Revised March 2011
Preface ....................................................................................................................................... 9
1 Introduction ...................................................................................................................... 13
1.1 Submodule Overview .................................................................................................. 13
1.2 Register Mapping ...................................................................................................... 17
2 ePWM Submodules ............................................................................................................ 20
2.1 Overview ................................................................................................................ 20
2.2 Time-Base (TB) Submodule .......................................................................................... 22
2.3 Counter-Compare (CC) Submodule ................................................................................. 33
2.4 Action-Qualifier (AQ) Submodule .................................................................................... 39
2.5 Dead-Band Generator (DB) Submodule ............................................................................ 53
2.6 PWM-Chopper (PC) Submodule ..................................................................................... 58
2.7 Trip-Zone (TZ) Submodule ........................................................................................... 62
2.8 Event-Trigger (ET) Submodule ....................................................................................... 67
2.9 Digital Compare (DC) Submodule ................................................................................... 71
3 Applications to Power Topologies ....................................................................................... 78
3.1 Overview of Multiple Modules ........................................................................................ 78
3.2 Key Configuration Capabilities ....................................................................................... 78
3.3 Controlling Multiple Buck Converters With Independent Frequencies .......................................... 79
3.4 Controlling Multiple Buck Converters With Same Frequencies .................................................. 83
3.5 Controlling Multiple Half H-Bridge (HHB) Converters ............................................................. 86
3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ................................................ 88
3.7 Practical Applications Using Phase Control Between PWM Modules .......................................... 92
3.8 Controlling a 3-Phase Interleaved DC/DC Converter ............................................................. 93
3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter ............................................. 97
3.10 Controlling a Peak Current Mode Controlled Buck Module ...................................................... 99
3.11 Controlling H-Bridge LLC Resonant Converter ................................................................... 101
4 Registers ........................................................................................................................ 104
4.1 Time-Base Submodule Registers .................................................................................. 104
4.2 Counter-Compare Submodule Registers .......................................................................... 111
4.3 Action-Qualifier Submodule Registers ............................................................................. 115
4.4 Dead-Band Submodule Registers .................................................................................. 118
4.5 PWM-Chopper Submodule Control Register ..................................................................... 120
4.6 Trip-Zone Submodule Control and Status Registers ............................................................ 122
4.7 Digital Compare Submodule Registers ............................................................................ 129
4.8 Event-Trigger Submodule Registers ............................................................................... 134
4.9 Proper Interrupt Initialization Procedure ........................................................................... 139
Appendix A Revision History ..................................................................................................... 140
3
SPRUGE9E–December 2008–Revised March 2011 Table of Contents
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© 2008–2011, Texas Instruments Incorporated
www.ti.com
List of Figures
1 Multiple ePWM Modules.................................................................................................. 15
2 Submodules and Signal Connections for an ePWM Module ........................................................ 16
3 ePWM Submodules and Critical Internal Signal Interconnects...................................................... 17
4 Time-Base Submodule Block Diagram ................................................................................. 22
5 Time-Base Submodule Signals and Registers ........................................................................ 23
6 Time-Base Frequency and Period ...................................................................................... 25
7 Time-Base Counter Synchronization Scheme 1 ...................................................................... 27
8 Time-Base Counter Synchronization Scheme 2 ...................................................................... 28
9 Time-Base Counter Synchronization Scheme 3 ...................................................................... 29
10 Time-Base Up-Count Mode Waveforms................................................................................ 31
11 Time-Base Down-Count Mode Waveforms ............................................................................ 32
12 Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event ..... 32
13 Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event......... 33
14 Counter-Compare Submodule ........................................................................................... 33
15 Detailed View of the Counter-Compare Submodule .................................................................. 35
16 Counter-Compare Event Waveforms in Up-Count Mode ............................................................ 37
17 Counter-Compare Events in Down-Count Mode ...................................................................... 38
18 Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event ................................................................................................... 39
19 Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ....................................................................................................................... 39
20 Action-Qualifier Submodule .............................................................................................. 40
21 Action-Qualifier Submodule Inputs and Outputs ...................................................................... 41
22 Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs............................................ 42
23 Up-Down-Count Mode Symmetrical Waveform ....................................................................... 45
24 Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................... 46
25 Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low.................................................................................................... 47
26 Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ............. 48
27 Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low .................................................................................................. 50
28 Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary ............................................................................................ 51
29 Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low .......................................................................................................................... 52
30 Dead_Band Submodule .................................................................................................. 53
31 Configuration Options for the Dead-Band Submodule ............................................................... 54
32 Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................... 56
33 PWM-Chopper Submodule............................................................................................... 58
34 PWM-Chopper Submodule Operational Details....................................................................... 59
35 Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ................................. 59
36 PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ........ 60
37 PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses....................................................................................................................... 61
38 Trip-Zone Submodule..................................................................................................... 62
39 Trip-Zone Submodule Mode Control Logic ............................................................................ 66
40 Trip-Zone Submodule Interrupt Logic................................................................................... 67
41 Event-Trigger Submodule ................................................................................................ 68
4
List of Figures SPRUGE9E–December 2008–Revised March 2011
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© 2008–2011, Texas Instruments Incorporated
www.ti.com
42 Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion......................................... 68
43 Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs......................................... 69
44 Event-Trigger Interrupt Generator....................................................................................... 70
45 Event-Trigger SOCA Pulse Generator.................................................................................. 71
46 Event-Trigger SOCB Pulse Generator.................................................................................. 71
47 Digital-Compare Submodule High-Level Block Diagram............................................................. 72
48 DCAEVT1 Event Triggering.............................................................................................. 74
49 DCAEVT2 Event Triggering.............................................................................................. 74
50 DCBEVT1 Event Triggering.............................................................................................. 75
51 DCBEVT2 Event Triggering.............................................................................................. 75
52 Event Filtering.............................................................................................................. 76
53 Blanking Window Timing Diagram ...................................................................................... 77
54 Simplified ePWM Module................................................................................................. 78
55 EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ....................................... 79
56 Control of Four Buck Stages. Here F
PWM1
≠ F
PWM2
≠ F
PWM3
≠ F
PWM4
.................................................... 80
57 Buck Waveforms for (Note: Only three bucks shown here).......................................................... 81
58 Control of Four Buck Stages. (Note: F
PWM2
= N x F
PWM1
).............................................................. 83
59 Buck Waveforms for (Note: F
PWM2
= F
PWM1)
)............................................................................. 84
60 Control of Two Half-H Bridge Stages (F
PWM2
= N x F
PWM1
) ............................................................ 86
61 Half-H Bridge Waveforms for (Note: Here F
PWM2
= F
PWM1
)............................................................ 87
62 Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................... 89
63 3-Phase Inverter Waveforms for (Only One Inverter Shown) ....................................................... 90
64 Configuring Two PWM Modules for Phase Control ................................................................... 92
65 Timing Waveforms Associated With Phase Control Between 2 Modules.......................................... 93
66 Control of a 3-Phase Interleaved DC/DC Converter.................................................................. 94
67 3-Phase Interleaved DC/DC Converter Waveforms for .............................................................. 95
68 Controlling a Full-H Bridge Stage (F
PWM2
= F
PWM1)
..................................................................... 97
69 ZVS Full-H Bridge Waveforms........................................................................................... 98
70 Peak Current Mode Control of a Buck Converter.................................................................... 100
71 Peak Current Mode Control Waveforms for ......................................................................... 100
72 Control of Two Resonant Converter Stages.......................................................................... 101
73 H-Bridge LLC Resonant Converter PWM Waveforms .............................................................. 102
74 Time-Base Period Register (TBPRD) ................................................................................. 104
75 Time Base Period High Resolution Register (TBPRDHR) ......................................................... 104
76 Time Base Period Mirror Register (TBPRDM) ....................................................................... 104
77 Time-Base Period High Resolution Mirror Register (TBPRDHRM) .............................................. 105
78 Time-Base Phase Register (TBPHS).................................................................................. 105
79 Time-Base Phase High Resolution Register (TBPHSHR).......................................................... 106
80 Time-Base Counter Register (TBCTR)................................................................................ 106
81 Time-Base Control Register (TBCTL) ................................................................................. 106
82 Time-Base Status Register (TBSTS).................................................................................. 109
83 High Resolution Period Control Register (HRPCTL) ................................................................ 109
84 Counter-Compare A Register (CMPA) ............................................................................... 111
85 Counter-Compare B Register (CMPB) ................................................................................ 111
86 Counter-Compare Control Register (CMPCTL)...................................................................... 113
87 Compare A High Resolution Register (CMPAHR) .................................................................. 114
88 Counter-Compare A Mirror Register (CMPAM) ..................................................................... 114
89 Compare A High Resolution Mirror Register ......................................................................... 114
90 Action-Qualifier Output A Control Register (AQCTLA).............................................................. 115
5
SPRUGE9E–December 2008–Revised March 2011 List of Figures
Submit Documentation Feedback
© 2008–2011, Texas Instruments Incorporated
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