s32v234芯片的开发手册_PS32V234CMVUB

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S32V234 Reference Manual

Document Number: S32V234RM

Rev. 2.3, 09/2017

Contents

Section number Title Page

Chapter 1

About This Manual

1.1 Audience....................................................................................................................................................................... 119

1.2 Organization..................................................................................................................................................................119

1.3 Module descriptions......................................................................................................................................................119

1.3.1 Example: chip-specific information that clarifies content in the same chapter........................................... 120

1.3.2 Example: chip-specific information that refers to a different chapter......................................................... 121

1.4 Register descriptions.....................................................................................................................................................122

1.5 Conventions.................................................................................................................................................................. 123

1.5.1 Notes, Cautions, and Warnings....................................................................................................................123

1.5.2 Numbering systems......................................................................................................................................123

1.5.3 Typographic notation................................................................................................................................... 124

1.5.4 Special terms................................................................................................................................................124

Chapter 2

Introduction

2.1 Introduction...................................................................................................................................................................127

2.1.1 Target applications.......................................................................................................................................128

2.1.2 Block diagram..............................................................................................................................................128

2.1.3 Device Configuration...................................................................................................................................128

2.1.4 Feature Set....................................................................................................................................................132

Chapter 3

Embedded Memory Overview

3.1 Memory structure..........................................................................................................................................................135

3.2 Attached peripheral memory map.................................................................................................................................137

3.3 VSEQ memory map......................................................................................................................................................137

3.4 Validation of error correction/detection........................................................................................................................137

Chapter 4

Memory Map

S32V234 Reference Manual, Rev. 2.3, 09/2017

NXP Semiconductors 3

Section number Title Page

4.1 Peripheral Memory Map...............................................................................................................................................139

4.2 Interrupt Map................................................................................................................................................................ 139

Chapter 5

Signal Description

5.1 Signal Description.........................................................................................................................................................141

5.1.1 Miscellaneous Pins.......................................................................................................................................141

5.1.2 I/O Behavior During Reset.......................................................................................................................... 142

5.2 RESET pin behaviour during selftest........................................................................................................................... 142

Chapter 6

ARM modules

6.1 Glossary........................................................................................................................................................................ 143

6.2 Platform components.................................................................................................................................................... 143

6.3 Cortex-A53 cluster complex.........................................................................................................................................145

6.3.1 ARM Cortex-A53 MPCore..........................................................................................................................146

6.3.2 ARM Generic Interrupt Controller (GIC-400).............................................................................................148

6.3.3 ARM CoreLink CCI-400 Cache Coherent Interconnect..............................................................................150

6.4 Cortex-M4 processor.................................................................................................................................................... 152

6.5 CoreLink Network Interconnect NIC-301....................................................................................................................152

6.6 Extended Resource Domain Controller (XRDC)......................................................................................................... 153

6.7 Operational details........................................................................................................................................................ 153

6.7.1 Cluster reset..................................................................................................................................................153

6.7.2 Cluster clock gating..................................................................................................................................... 153

Chapter 7

Enhanced Direct Memory Access (eDMA)

7.1 Chip specific eDMA information................................................................................................................................. 155

7.2 Introduction...................................................................................................................................................................155

7.2.1 eDMA system block diagram...................................................................................................................... 155

7.2.2 Block parts................................................................................................................................................... 156

7.2.3 Features........................................................................................................................................................ 157

7.3 Modes of operation....................................................................................................................................................... 158

S32V234 Reference Manual, Rev. 2.3, 09/2017

4 NXP Semiconductors

Section number Title Page

7.4 Memory map/register definition................................................................................................................................... 159

7.4.1 TCD memory............................................................................................................................................... 159

7.4.2 TCD initialization........................................................................................................................................ 159

7.4.3 TCD structure...............................................................................................................................................159

7.4.4 Reserved memory and bit fields...................................................................................................................160

7.4.5 Control Register (DMA_CR).......................................................................................................................182

7.4.6 Error Status Register (DMA_ES)................................................................................................................ 185

7.4.7 Enable Request Register (DMA_ERQ)....................................................................................................... 188

7.4.8 Enable Error Interrupt Register (DMA_EEI)...............................................................................................191

7.4.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 195

7.4.10 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 196

7.4.11 Clear Enable Request Register (DMA_CERQ)...........................................................................................197

7.4.12 Set Enable Request Register (DMA_SERQ)...............................................................................................198

7.4.13 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................199

7.4.14 Set START Bit Register (DMA_SSRT)...................................................................................................... 200

7.4.15 Clear Error Register (DMA_CERR)............................................................................................................201

7.4.16 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 202

7.4.17 Interrupt Request Register (DMA_INT)......................................................................................................203

7.4.18 Error Register (DMA_ERR)........................................................................................................................ 206

7.4.19 Hardware Request Status Register (DMA_HRS)........................................................................................ 210

7.4.20

General-Purpose Output Register (DMA_GPORn).....................................................................................216

7.4.21

Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 217

7.4.22

Channel n Master ID Register (DMA_DCHMIDn).................................................................................... 218

7.4.23

TCD Source Address (DMA_TCDn_SADDR)...........................................................................................219

7.4.24

TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................219

7.4.25