4 UART PHYSICAL LAYER
1 Revisions
5 June 16, 2018 add I2SE address, add example ethernet frame, fix frame
offset in UART transmit description
4 February 7, 2017 additionally describe UART interface to QCA7000
3 April 1, 2016 add SPI data width, add diagrams, add OSI model, fix ini-
tial setup fix interrupt handling, avoid misunderstandings
2 April 21, 2015 added SPI CLK speed, changed EOF fields of transmit
frames to length 2
1 September 30, 2014 initial release
2 Introduction
This application note aims to describe the QCA7000 PLC Chip SPI / UART interface. The documentation was
derived from the original Qualcomm Atheros Linux driver for the QCA7000, which was initially published at https:
//github.com/IoE/qca7000. All information within this document can be derived from this code.
The basis for this document is the status of the driver at the time this document was released initially. It’s focus is
on layers 1 and 2 of the OSI model.
OSI layer Protocol Software component
7 - Application Application Application
6 - Presentation
5 - Session
4 - Transport TCP / UDP TCP / UDP stack
3 - Network IP v4 / v6 IP stack
2 - Data link Ethernet Ethernet over SPI / UART protocol driver
1 - Physical SPI / UART SPI / UART driver
I2SE GmbH does not give any free support for driver development. Please contact us if you want to know conditions
of our paid support.
Note: During development we strongly suggest to have a logic analyzer with the following features:
• at least 5 channels
• at least 24 MHz sampling rate
• SPI / UART decoding
3 SPI Physical Layer
The QCA7000 acts as a SPI slave and uses Mode 3: CPOL=1, CPHA=1.
SPI data width is 8 bit. The SPI CLK period should not be less than 83.3 ns.
The SPI should be used in burst mode, meaning that the chip select is held low during a complete SPI message.
Note: The SPI lines between Host CPU and QCA7000 should be kept as short as possible.
4 UART Physical Layer
The QCA7000 has a 4 wire UART interface (TX, RX, CTS, RTS) where the hardware flow control is optional.
Several UART settings are possible and are configurable with tools that are available under NDA from Qualcomm.
I2SE chose the settings in Table 4 as a default for all UART interfaced modules.
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