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i.MX 8QuadMax Applications

Processor Reference Manual

Document Number: IMX8QMRM

Rev. E, 06/2018

Preliminary

Confidential Proprietary

Contents

Section number Title Page

Chapter 1

Overview

1.1 Introduction...................................................................................................................................................................9

1.2 Architectual Overview..................................................................................................................................................15

Chapter 2

Memory Map

2.1 Overview.......................................................................................................................................................................19

2.2 System Memory Map....................................................................................................................................................20

Chapter 3

Memory and Interrupt Interfaces

3.1 Memory and Interrupt Interfaces.................................................................................................................................. 49

3.2 Interrupt Maps...............................................................................................................................................................57

3.3 Interrupt Request Steering (IRQ_STEER)....................................................................................................................77

3.4 Interrupt Multiplexer (INTMUX).................................................................................................................................87

Chapter 4

System Security

4.1 Overview.......................................................................................................................................................................97

Chapter 5

System Boot

5.1 Overview.......................................................................................................................................................................105

5.2 Terms............................................................................................................................................................................ 106

5.3 Boot modes................................................................................................................................................................... 108

5.4 High Level Boot Flow.................................................................................................................................................. 110

5.5 Secure Boot Flow with SCU and SECO.......................................................................................................................113

5.6 Standard Boot Flow Use Case...................................................................................................................................... 114

5.7 Device Configuration....................................................................................................................................................116

5.8 Boot Devices.................................................................................................................................................................122

5.9 Boot image....................................................................................................................................................................159

i.MX 8QuadMax Applications Processor Reference Manual, Rev. E, 06/2018

NXP Semiconductors

Preliminary

Confidential Proprietary

Section number Title Page

5.10 Serial Downloader Boot................................................................................................................................................177

5.11 SD/MMC manufacture mode........................................................................................................................................179

5.12 Handover and Passover for SCFW and AP IPL/Bootloader........................................................................................ 179

Chapter 6

Debug Architecture

6.1 Chip debug architecture................................................................................................................................................ 185

6.2 JTAG topology..............................................................................................................................................................186

Chapter 7

Fusemap

7.1 Overview.......................................................................................................................................................................191

7.2 Fusemap........................................................................................................................................................................193

Chapter 8

Chip IO

8.1 External Signals and Pin Assignments......................................................................................................................... 203

8.2 IOMUXD...................................................................................................................................................................... 225

Chapter 9

DRAM Subsystem

9.1 DRC Overview..............................................................................................................................................................803

9.2 DDR Performance Monitor (DDR_PERF_MON)........................................................................................................803

9.3 DDR Controller (DDRC)..............................................................................................................................................816

9.4 DDR Phy (DDRP).........................................................................................................................................................1014

Chapter 10

ARM AP Subsystem

10.1 ARM AP Complex........................................................................................................................................................1871

Chapter 11

ARM Cortex-M4 (CM4) Subsystem

11.1 ARM Cortex-M4 Complex...........................................................................................................................................1891

11.2 ARM Cortex M4 Platform (M4)...................................................................................................................................1901

11.3 Low Power Inter-Integrated Circuit (LPI2C)............................................................................................................... 1936

11.4 Low Power Periodic Interrupt Timer (LPIT)................................................................................................................1992

i.MX 8QuadMax Applications Processor Reference Manual, Rev. E, 06/2018

Preliminary

NXP Semiconductors

Confidential Proprietary

Section number Title Page

11.5 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)..................................................................... 2028

11.6 Rapid General-Purpose Input and Output (RGPIO)..................................................................................................... 2072

11.7 Low Power Timer/Pulse Width Modulation Module (TPM)....................................................................................... 2082

11.8 Semaphores2 (SEMA42).............................................................................................................................................. 2132

11.9 Watchdog Timer (WDOG)........................................................................................................................................... 2142

Chapter 12

System Controller Unit (SCU)

12.1 System Controller Overview.........................................................................................................................................2159

12.2 JTAG Controller (JTAGC)........................................................................................................................................... 2176

12.3 Low Power Inter-Integrated Circuit (LPI2C)............................................................................................................... 2188

12.4 Low Power Periodic Interrupt Timer (LPIT)................................................................................................................2244

12.5 Low Power Timer/Pulse Width Modulation Module (TPM)....................................................................................... 2280

12.6 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)..................................................................... 2329

12.7 Rapid General-Purpose Input and Output (RGPIO)..................................................................................................... 2373

12.8 Semaphores2 (SEMA42).............................................................................................................................................. 2383

12.9 Watchdog Timer (WDOG)........................................................................................................................................... 2394

12.10 SCU Low Power Controller (SCU_LPC).....................................................................................................................2411

12.11 On-Chip OTP Controller (OCOTP_CTRL)..................................................................................................................2420

Chapter 13

Connectivity Subsystem

13.1 Connectivity Overview ................................................................................................................................................ 3219

13.2 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA).......................................................................................... 3223

13.3 62BIT Correcting ECC Accelerator (BCH)..................................................................................................................3293

13.4 MediaLB (MLB)...........................................................................................................................................................3373

13.5 Enhanced Direct Memory Access (eDMA)..................................................................................................................3427

13.6 Ethernet MAC (ENET).................................................................................................................................................3493

13.7 General Purpose Media Interface (GPMI)....................................................................................................................3667

13.8 Ultra Secured Digital Host Controller (uSDHC)..........................................................................................................3753

13.9 USB Device Charger Detection Module (USBDCD)...................................................................................................3884

i.MX 8QuadMax Applications Processor Reference Manual, Rev. E, 06/2018

NXP Semiconductors

Preliminary

Confidential Proprietary