没有合适的资源?快使用搜索试试~ 我知道了~
首页DDR3 JEDEC 官方标准文档
DDR3 JEDEC 官方标准文档
5星 · 超过95%的资源 需积分: 45 232 下载量 199 浏览量
更新于2023-03-16
评论 9
收藏 10.66MB PDF 举报
DDR3 JEDEC 官方标准文档 DDR3 JEDEC 官方标准文档 DDR3 JEDEC 官方标准文档
资源详情
资源评论
资源推荐
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD79-3F
J 2012
JEDEC
STANDARD
DDR3 SDRAM S
(Revision of JESD79-3E, July 2010)
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
publication may be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or
www.jedec.org
Published by
©JEDEC Solid State Technology Association 2012
3103 North 10th Street, Suite 240 South
Arlington, VA 22201
This document may be downloaded free of charge; however JEDEC retains the copyright on this
material. By downloading this file the individual agrees not to charge for or resell the resulting
material.
PRICE: Please refer to the current
Catalog of JEDEC Engineering Standards and Publications online at
http://www.jedec.org/Catalog/catalog.cfm
Printed in the U.S.A.
All rights reserved
PLEASE!
DON'T VIOLATE THE LAW!
This document is copyrighted by JEDEC and may not be
reproduced without permission.
Organizations may obtain permission to reproduce a limited number of copies
through entering into a license agreement. For information, contact:
JEDEC Solid State Technology Association
3103 North 10th Street, Suite 240 South
Arlington, Virginia 22201
or call (703) 907-7559
This page left blank.
JEDEC Standard No. 79-3F
Contents
i
1 Scope..........................................................................................................................................1
2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
2.1 DDR3 SDRAM x4 Ballout using MO-207........................................................................3
2.11.1 512Mb ....................................................................................................................15
2.11.2 1Gb..........................................................................................................................15
2.11.3 2Gb .........................................................................................................................15
2.11.4 4Gb .........................................................................................................................15
2.11.5 8Gb .........................................................................................................................16
3 Functional Description.............................................................................................................17
3.1 Simplified State Diagram.................................................................................................17
3.3.1 Power-up Initialization Sequence .............................................................................19
3.3.2 Reset Initialization with Stable Power......................................................................21
3.4.1 Programming the Mode Registers ............................................................................22
3.4.2 Mode Register MR0..................................................................................................23
3.4.3 Mode Register MR1..................................................................................................27
3.4.4 Mode Register MR2..................................................................................................30
3.4.5 Mode Register MR3..................................................................................................32
4 DDR3 SDRAM Command Description and Operation...........................................................33
4.1 Command Truth Table .....................................................................................................33
4.3 No OPeration (NOP) Command ......................................................................................36
4.4 Deselect Command ..........................................................................................................36
4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38
4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39
4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43
4.8.2 Procedure Description...............................................................................................43
4.8.3 Write Leveling Mode Exit ........................................................................................45
4.9.1 Self-Refresh Temperature Range - SRT...................................................................46
4.10.1 MPR Functional Description ..................................................................................49
4.10.2 MPR Register Address Definition ..........................................................................50
4.10.3 Relevant Timing Parameters...................................................................................50
4.10.4 Protocol Example....................................................................................................50
4.12 PRECHARGE Command ..............................................................................................55
4.13.1 READ Burst Operation...........................................................................................56
4.13.3 Burst Read Operation followed by a Precharge......................................................66
4.14.1 DDR3 Burst Operation ...........................................................................................68
4.14.2 WRITE Timing Violations .....................................................................................68
4.14.3 Write Data Mask.....................................................................................................69
4.14.4 tWPRE Calculation.................................................................................................70
4.14.5 tWPST Calculation .................................................................................................70
4.17.1 Power-Down Entry and Exit...................................................................................81
4.17.2 Power-Down clarifications - Case 1 .......................................................................86
4.17.3 Power-Down clarifications - Case 2 .......................................................................87
5 On-Die Termination (ODT).....................................................................................................89
5.1 ODT Mode Register and ODT Truth Table.....................................................................89
剩余225页未读,继续阅读
mokedeng
- 粉丝: 1
- 资源: 9
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- 27页智慧街道信息化建设综合解决方案.pptx
- 计算机二级Ms-Office选择题汇总.doc
- 单链表的插入和删除实验报告 (2).docx
- 单链表的插入和删除实验报告.pdf
- 物联网智能终端项目设备管理方案.pdf
- 如何打造品牌的模式.doc
- 样式控制与页面布局.pdf
- 武汉理工Java实验报告(二).docx
- 2021线上新品消费趋势报告.pdf
- 第3章 Matlab中的矩阵及其运算.docx
- 基于Web的人力资源管理系统的必要性和可行性.doc
- 基于一阶倒立摆的matlab仿真实验.doc
- 速运公司物流管理模式研究教材
- 大数据与管理.pptx
- 单片机课程设计之步进电机.doc
- 大数据与数据挖掘.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论6