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PCI Express
®
Base Specification
Revision 4.0 Version 0.3
February 19, 2014
2
Revision Revision History DATE
1.0
Initial release.
07/22/2002
1.0a
Incorporated Errata C1-C66 and E1-E4.17.
04/15/2003
1.1
Incorporated approved Errata and ECNs.
03/28/2005
2.0
Added 5.0 GT/s data rate and incorporated approved Errata and ECNs.
12/20/2006
2.1 Incorporated Errata for the PCI Express Base Specification, Rev. 2.0
(February 27, 2009), and added the following ECNs:
• Internal Error Reporting ECN (April 24, 2008)
• Multicast ECN (December 14, 2007, approved by PWG May 8, 2008)
• Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008)
• Resizable BAR Capability ECN (January 22, 2008, updated and approved by
PWG April 24, 2008)
• Dynamic Power Allocation ECN (May 24, 2008)
• ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008)
• Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008)
• Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated
June 4, 2007)
• Extended Tag Enable Default ECN (September 5, 2008)
• TLP Processing Hints ECN (September 11, 2008)
•
TLP Prefix ECN (December 15, 2008)
03/04/2009
3.0
Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs:
• Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009)
• ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009)
• Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol
Multiplexing ECN (17 June 2010)
11/10/2010
3.1 Incorporated Errata for the PCI Express® Base Specification Revision 3.0
(November 7, 2013)
Incorporated the following ECNs:
• ECN: Downstream Port containment (DPC)
• ECN: Separate Refclk Independent SSC (SRIS) Architecture
• ECN: Process Address Space ID (PASID)
• ECN: Lightweight Notification (LN) Protocol
• ECN: Precision Time Measurement
• ECN: Enhanced DPC (eDPC)
• ECN: 8.0 GT/s Receiver Impedance
• ECN: L1 PM Substates with CLKREQ
• ECN: Change Root Complex Event Collector Class Code
• ECN: M-PCIe
•
ECN: Readiness Notifications (RN)
11/7/2013
4.0
Version 0.3: Based on PCI Express® Base Specification Revision 3.1
(November 7, 2013) with some editorial feedback received in December 2013.
• Added Chapter 9, Electrical Sub-block: Separated Section 4.3 of the 3.1 Base
Specification to create Chapter 9.Added Chapter 9 (Rev0.3-11-30-13_final.docx)
• Changes related to Revision 0.3 release
•
2/19/2014
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3
3
PCI-SIG
®
disclaims all warranties and liability for the use of this document and the information contained herein and
assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to
update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of this specification.
Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to:
Membership Services
www.pcisig.com
E-mail: administration@pcisig.com
Phone: 503-619-0569
Fax: 503-644-6708
Technical Support
techsupp@pcisig.com
DISCLAIMER
This PCI Express Base Specification is provided “as is” with no warranties whatsoever, including any warranty of
merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any
proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to
use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted herein.
PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.
All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
Copyright © 2002-2014 PCI-SIG
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3
4
Contents
OBJECTIVE OF THE SPECIFICATION ............................................................................... 35
DOCUMENT ORGANIZATION.............................................................................................. 35
DOCUMENTATION CONVENTIONS ................................................................................... 35
TERMS AND ACRONYMS ...................................................................................................... 36
REFERENCE DOCUMENTS ................................................................................................... 44
1. INTRODUCTION............................................................................................................... 46
1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 46
1.2. PCI EXPRESS LINK ......................................................................................................... 49
1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 50
Root Complex ........................................................................................................ 50 1.3.1.
Endpoints .............................................................................................................. 51 1.3.2.
Switch .................................................................................................................... 54 1.3.3.
Root Complex Event Collector .............................................................................. 55 1.3.4.
PCI Express to PCI/PCI-X Bridge ........................................................................ 55 1.3.5.
1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 55
1.5. PCI EXPRESS LAYERING OVERVIEW .............................................................................. 56
Transaction Layer ................................................................................................. 57 1.5.1.
Data Link Layer .................................................................................................... 57 1.5.2.
Physical Layer ...................................................................................................... 58 1.5.3.
Layer Functions and Services ............................................................................... 58 1.5.4.
2.
TRANSACTION LAYER SPECIFICATION ................................................................. 62
2.1. TRANSACTION LAYER OVERVIEW .................................................................................. 62
Address Spaces, Transaction Types, and Usage ................................................... 63 2.1.1.
Packet Format Overview ...................................................................................... 65 2.1.2.
2.2.
TRANSACTION LAYER PROTOCOL - PACKET DEFINITION ............................................... 67
Common Packet Header Fields ............................................................................ 67 2.2.1.
TLPs with Data Payloads - Rules ......................................................................... 70 2.2.2.
TLP Digest Rules .................................................................................................. 74 2.2.3.
Routing and Addressing Rules .............................................................................. 74 2.2.4.
First/Last DW Byte Enables Rules ........................................................................ 78 2.2.5.
Transaction Descriptor ......................................................................................... 81 2.2.6.
Memory, I/O, and Configuration Request Rules ................................................... 87 2.2.7.
Message Request Rules ......................................................................................... 94 2.2.8.
Completion Rules ................................................................................................ 115 2.2.9.
TLP Prefix Rules ................................................................................................. 118 2.2.10.
2.3. HANDLING OF RECEIVED TLPS .................................................................................... 123
Request Handling Rules ...................................................................................... 126 2.3.1.
Completion Handling Rules ................................................................................ 138 2.3.2.
2.4. TRANSACTION ORDERING ............................................................................................ 142
Transaction Ordering Rules ............................................................................... 142 2.4.1.
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3
5
Update Ordering and Granularity Observed by a Read Transaction ................ 145 2.4.2.
Update Ordering and Granularity Provided by a Write Transaction ................ 146 2.4.3.
2.5. VIRTUAL CHANNEL (VC) MECHANISM ........................................................................ 147
Virtual Channel Identification (VC ID) .............................................................. 149 2.5.1.
TC to VC Mapping .............................................................................................. 150 2.5.2.
VC and TC Rules ................................................................................................. 151 2.5.3.
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 152
Flow Control Rules ............................................................................................. 153 2.6.1.
2.7. DATA INTEGRITY ......................................................................................................... 164
ECRC Rules ........................................................................................................ 165 2.7.1.
Error Forwarding ............................................................................................... 169 2.7.2.
2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 171
2.9. LINK STATUS DEPENDENCIES ...................................................................................... 172
Transaction Layer Behavior in DL_Down Status ............................................... 172 2.9.1.
Transaction Layer Behavior in DL_Up Status ................................................... 173 2.9.2.
Transaction Layer Behavior During Downstream Port Containment ............... 174 2.9.3.
3. DATA LINK LAYER SPECIFICATION ...................................................................... 176
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 176
3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 178
Data Link Control and Management State Machine Rules ................................ 179 3.2.1.
3.3.
FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 181
Flow Control Initialization State Machine Rules ............................................... 182 3.3.1.
3.4. DATA LINK LAYER PACKETS (DLLPS) ........................................................................ 185
Data Link Layer Packet Rules ............................................................................ 185 3.4.1.
3.5. DATA INTEGRITY ......................................................................................................... 190
Introduction......................................................................................................... 190 3.5.1.
LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 190 3.5.2.
LCRC and Sequence Number (TLP Receiver) .................................................... 203 3.5.3.
4. PHYSICAL LAYER SPECIFICATION ........................................................................ 213
4.1. INTRODUCTION ............................................................................................................ 213
4.2. LOGICAL SUB-BLOCK ................................................................................................... 213
Encoding for 2.5 GT/s and 5.0 GT/s Data Rates ................................................ 214 4.2.1.
Encoding for 8.0 GT/s and Higher Data Rates................................................... 222 4.2.2.
Link Equalization Procedure for 8.0 GT/s and Higher Data Rates ................... 241 4.2.3.
Link Initialization and Training .......................................................................... 251 4.2.4.
Link Training and Status State Machine (LTSSM) Descriptions ........................ 270 4.2.5.
Link Training and Status State Rules .................................................................. 273 4.2.6.
Clock Tolerance Compensation .......................................................................... 342 4.2.7.
Compliance Pattern in 8b/10b Encoding ............................................................ 347 4.2.8.
Modified Compliance Pattern in 8b/10b Encoding ............................................ 348 4.2.9.
Compliance Pattern in 128b/130b Encoding ...................................................... 350 4.2.10.
Modified Compliance Pattern in 128b/130b Encoding ...................................... 352 4.2.11.
5. POWER MANAGEMENT .............................................................................................. 353
5.1. OVERVIEW ................................................................................................................... 353
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