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TDA3x

SoC for Advanced Driver Assistance

Systems (ADAS)

Silicon Revision 2.0, 1.0A, 1.0

Texas Instruments ADAS Family of Products

Technical Reference Manual

Literature Number: SPRUIE7A

June 2017–Revised October 2017

SPRUIE7A–June 2017–Revised October 2017

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Contents

Revision History ........................................................................................................................ 315

Preface..................................................................................................................................... 316

1 Introduction ..................................................................................................................... 323

1.1 TDA3x Overview .......................................................................................................... 324

1.2 TDA3x Environment ...................................................................................................... 326

1.3 TDA3x Description........................................................................................................ 327

1.3.1 Block Diagram.................................................................................................... 327

1.3.2 MCU Subsystem ................................................................................................. 328

1.3.3 DSP Subsystem.................................................................................................. 328

1.3.4 EVE Subsystem.................................................................................................. 328

1.3.5 Imaging Subsystem.............................................................................................. 329

1.3.6 Video Input Capture ............................................................................................. 330

1.3.7 Display Subsystem .............................................................................................. 330

1.3.8 On-Chip Debug Support ........................................................................................ 331

1.3.9 On-Chip Memory................................................................................................. 331

1.3.10 Memory Management .......................................................................................... 331

1.3.11 External Memory Interfaces ................................................................................... 331

1.3.12 Power, Reset, and Clock Management...................................................................... 332

1.3.13 System and Connectivity Peripherals ........................................................................ 332

1.3.13.1 System Peripherals........................................................................................ 332

1.3.13.2 Connectivity Peripherals.................................................................................. 333

1.3.13.3 Serial Control Peripherals ................................................................................ 333

1.4 TDA3x Family ............................................................................................................. 334

1.5 TDA3x Device Identification ............................................................................................. 334

1.6 TDA3x Package Characteristics Overview ............................................................................ 336

2 Memory Mapping .............................................................................................................. 337

2.1 Introduction ................................................................................................................ 338

2.2 L3_MAIN Memory Map .................................................................................................. 340

2.2.1 L3_INSTR Memory Map ........................................................................................ 342

2.3 L4 Memory Map........................................................................................................... 344

2.3.1 L4_CFG Memory Map .......................................................................................... 344

2.3.2 L4_WKUP Memory Map ........................................................................................ 346

2.4 L4_PER Memory Map.................................................................................................... 347

2.4.1 L4_PER1 Memory Space Mapping............................................................................ 347

2.4.2 L4_PER2 Memory Map ......................................................................................... 349

2.4.3 L4_PER3 Memory Map ......................................................................................... 350

2.5 IPU Memory Map ......................................................................................................... 352

2.6 DSP Memory Map ........................................................................................................ 354

2.7 EVE Memory Map ........................................................................................................ 355

3 Power, Reset, and Clock Management................................................................................. 356

3.1 Device Power Management Introduction .............................................................................. 357

3.1.1 Device Power-Management Architecture Building Blocks.................................................. 358

3.1.1.1 Clock Management........................................................................................ 358

3.1.1.1.1 Module Interface and Functional Clocks........................................................... 358

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Contents

3.1.1.1.2 Module-Level Clock Management .................................................................. 359

3.1.1.1.3 Clock Domain.......................................................................................... 364

3.1.1.1.4 Clock Domain-Level Clock Management .......................................................... 365

3.1.1.1.5 Clock Domain HW_AUTO Mode Sequences ..................................................... 366

3.1.1.1.6 Clock Domain Sleep/Wake-up ...................................................................... 369

3.1.1.1.7 Clock Domain Dependency.......................................................................... 370

3.1.1.2 Power Management....................................................................................... 376

3.1.1.2.1 Power Domain......................................................................................... 376

3.1.1.2.2 Module Logic and Memory Context ................................................................ 378

3.1.1.2.3 Power Domain Management ........................................................................ 378

3.1.1.3 Voltage Management ..................................................................................... 380

3.1.1.3.1 Voltage Domain ....................................................................................... 380

3.1.1.3.2 Voltage Domain Management....................................................................... 381

3.1.1.3.3 AVS Overview ......................................................................................... 382

3.1.2 Power-Management Techniques .............................................................................. 384

3.1.2.1 Standby Leakage Management ......................................................................... 384

3.1.2.2 Dynamic Voltage and Frequency Scaling .............................................................. 384

3.1.2.3 Dynamic Power Switching................................................................................ 385

3.1.2.4 Adaptive Voltage Scaling................................................................................. 386

3.1.2.5 Combining Power-Management Techniques .......................................................... 386

3.1.2.5.1 DPS Versus SLM ..................................................................................... 387

3.2 PRCM Subsystem Overview ............................................................................................ 388

3.2.1 Introduction ....................................................................................................... 388

3.2.2 Power-Management Framework Features ................................................................... 389

3.3 PRCM Subsystem Environment ........................................................................................ 391

3.3.1 External Clock Signals .......................................................................................... 391

3.3.2 External Boot Signals ........................................................................................... 391

3.3.3 External Reset Signals.......................................................................................... 391

3.3.4 External Voltage Inputs ......................................................................................... 392

3.4 PRCM Subsystem Integration........................................................................................... 393

3.4.1 Device Power-Management Layout ........................................................................... 393

3.4.2 Power-Management Scheme, Reset, and Interrupt Requests............................................. 395

3.4.2.1 Power Domain ............................................................................................. 395

3.4.2.2 Resets....................................................................................................... 395

3.4.2.3 PRCM Interrupt Requests ................................................................................ 396

3.5 Reset Management Functional Description ........................................................................... 397

3.5.1 Overview .......................................................................................................... 397

3.5.1.1 Reset Management Functional Description............................................................ 397

3.5.1.1.1 Power-On Reset ...................................................................................... 397

3.5.1.1.2 Warm Reset ........................................................................................... 397

3.5.1.2 PRM Reset Management Functional Description ..................................................... 397

3.5.2 General Characteristics of Reset Signals .................................................................... 397

3.5.2.1 Scope ....................................................................................................... 398

3.5.2.2 Occurrence ................................................................................................. 398

3.5.2.3 Source Type................................................................................................ 398

3.5.2.4 Retention Type............................................................................................. 398

3.5.3 Reset Sources.................................................................................................... 399

3.5.3.1 Global Reset Sources..................................................................................... 399

3.5.3.2 Local Reset Sources ...................................................................................... 399

3.5.4 Reset Logging.................................................................................................... 400

3.5.5 Reset Domains................................................................................................... 400

3.5.6 Reset Sequences................................................................................................ 411

3.5.6.1 IPU1 Subsystem Power-On Reset Sequence ......................................................... 411

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Contents

3.5.6.2 DSP1 Subsystem Power-On Reset Sequence ........................................................ 412

3.5.6.3 DSP1 Subsystem Software Warm Reset Sequence.................................................. 413

3.5.6.4 DSP2 Subsystem Power-On Reset Sequence ........................................................ 414

3.5.6.5 DSP2 Subsystem Software Warm Reset Sequence.................................................. 414

3.5.6.6 EVE Subsystem Power-On Reset Sequence.......................................................... 415

3.5.6.7 EVE Subsystem Software Warm Reset Sequence ................................................... 416

3.5.6.8 Global Warm Reset Sequence .......................................................................... 416

3.6 Clock Management Functional Description ........................................................................... 419

3.6.1 Overview .......................................................................................................... 419

3.6.2 External Clock Inputs............................................................................................ 419

3.6.2.1 High-Frequency System Clock Input.................................................................... 419

3.6.2.2 External Reference Clock Input ......................................................................... 420

3.6.3 Internal Clock Sources/Generators............................................................................ 420

3.6.3.1 PRM Clock Source ........................................................................................ 420

3.6.3.2 CM Clock Source.......................................................................................... 422

3.6.3.2.1 CM_CORE_AON Clock Generator ................................................................. 422

3.6.3.2.2 CM_CORE_AON_CLKOUTMUX Overview ....................................................... 428

3.6.3.2.3 CM_CORE_AON_TIMER Overview ............................................................... 432

3.6.3.2.4 CM_CORE_AON_MCASP1 Overview ............................................................ 433

3.6.3.3 Clock Control in Control Module......................................................................... 436

3.6.3.3.1 Programming Guide For Control Module .......................................................... 438

3.6.3.4 Generic DPLL Overview .................................................................................. 439

3.6.3.4.1 DPLLs Output Clocks Parameters.................................................................. 439

3.6.3.4.2 Enable Control, Status, and Low-Power Operation Mode....................................... 441

3.6.3.4.3 DPLL Power Modes .................................................................................. 441

3.6.3.4.4 DPLL Recalibration ................................................................................... 442

3.6.3.4.5 DPLL Output Power Down........................................................................... 443

3.6.3.5 DPLL_PER Description................................................................................... 444

3.6.3.5.1 DPLL_PER Overview................................................................................. 444

3.6.3.5.2 DPLL_PER Synthesized Clock Parameters....................................................... 444

3.6.3.5.3 DPLL_PER Power Modes ........................................................................... 445

3.6.3.5.4 DPLL_PER Recalibration ............................................................................ 445

3.6.3.6 DPLL_CORE Description................................................................................. 446

3.6.3.6.1 DPLL_CORE Overview .............................................................................. 446

3.6.3.6.2 DPLL_CORE Synthesized Clock Parameters..................................................... 446

3.6.3.6.3 DPLL_CORE Power Modes ......................................................................... 447

3.6.3.6.4 DPLL_CORE Recalibration.......................................................................... 448

3.6.3.6.5 Fractional M-factor (SR2.0).......................................................................... 448

3.6.3.7 DPLL_EVE_VID_DSP Description ...................................................................... 448

3.6.3.7.1 DPLL_EVE_VID_DSP Overview.................................................................... 448

3.6.3.7.2 DPLL_EVE_VID_DSP Synthesized Clock Parameters .......................................... 448

3.6.3.7.3 DPLL_EVE_VID_DSP Power Modes .............................................................. 449

3.6.3.7.4 DPLL_EVE_VID_DSP Recalibration ............................................................... 449

3.6.3.8 DPLL_GMAC_DSP Description ......................................................................... 450

3.6.3.8.1 DPLL_GMAC_DSP Overview ....................................................................... 450

3.6.3.8.2 DPLL_GMAC_DSP Synthesized Clock Parameters ............................................. 450

3.6.3.8.3 DPLL_GMAC_DSP Power Modes.................................................................. 451

3.6.3.8.4 DPLL_GMAC_DSP Recalibration................................................................... 451

3.6.3.9 DPLL_DDR Description................................................................................... 452

3.6.3.9.1 DPLL_DDR Overview ................................................................................ 452

3.6.3.9.2 DPLL_DDR Synthesized Clock Parameters....................................................... 452

3.6.3.9.3 DPLL_DDR Power Modes ........................................................................... 452

3.6.3.9.4 DPLL_DDR Recalibration............................................................................ 453

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Contents

3.6.4 Clock Domains ................................................................................................... 453

3.6.4.1 CD_WKUPAON Clock Domain .......................................................................... 453

3.6.4.1.1 Overview ............................................................................................... 453

3.6.4.1.2 Clock Domain Modes................................................................................. 454

3.6.4.1.3 Clock Domain Dependency.......................................................................... 455

3.6.4.1.4 Clock Domain Module Attributes.................................................................... 455

3.6.4.2 CD_DSP1 Clock Domain................................................................................. 457

3.6.4.2.1 Overview ............................................................................................... 457

3.6.4.2.2 Clock Domain Modes................................................................................. 458

3.6.4.2.3 Clock Domain Dependency.......................................................................... 458

3.6.4.2.4 Clock Domain Module Attributes.................................................................... 459

3.6.4.3 CD_DSP2 Clock Domain................................................................................. 459

3.6.4.3.1 Overview ............................................................................................... 459

3.6.4.3.2 Clock Domain Modes................................................................................. 460

3.6.4.3.3 Clock Domain Dependency.......................................................................... 460

3.6.4.3.4 Clock Domain Module Attributes.................................................................... 461

3.6.4.4 CD_CUSTEFUSE Clock Domain........................................................................ 462

3.6.4.4.1 Overview ............................................................................................... 462

3.6.4.4.2 Clock Domain Modes................................................................................. 462

3.6.4.4.3 Clock Domain Dependency.......................................................................... 463

3.6.4.4.4 Clock Domain Module Attributes.................................................................... 463

3.6.4.5 CD_L4PER1 Clock Domain.............................................................................. 463

3.6.4.5.1 Overview ............................................................................................... 463

3.6.4.5.2 Clock Domain Modes................................................................................. 464

3.6.4.5.3 Clock Domain Dependency.......................................................................... 465

3.6.4.5.4 Clock Domain Module Attributes.................................................................... 472

3.6.4.6 CD_L4PER2 Clock Domain.............................................................................. 475

3.6.4.6.1 Overview ............................................................................................... 475

3.6.4.6.2 Clock Domain Modes................................................................................. 475

3.6.4.6.3 Clock Domain Dependency.......................................................................... 476

3.6.4.6.4 Clock Domain Module Attributes.................................................................... 478

3.6.4.7 CD_L4PER3 Clock Domain.............................................................................. 480

3.6.4.7.1 Overview ............................................................................................... 480

3.6.4.7.2 Clock Domain Modes................................................................................. 481

3.6.4.7.3 Clock Domain Dependency.......................................................................... 481

3.6.4.7.4 Clock Domain Module Attributes.................................................................... 481

3.6.4.8 CD_L3INIT Clock Domain................................................................................ 482

3.6.4.8.1 Overview ............................................................................................... 482

3.6.4.8.2 Clock Domain Modes................................................................................. 483

3.6.4.8.3 Clock Domain Dependency.......................................................................... 483

3.6.4.8.4 Clock Domain Module Attributes.................................................................... 484

3.6.4.9 CD_EMU Clock Domain .................................................................................. 485

3.6.4.9.1 Overview ............................................................................................... 485

3.6.4.9.2 Clock Domain Modes................................................................................. 485

3.6.4.9.3 Clock Domain Dependency.......................................................................... 485

3.6.4.9.4 Clock Domain Module Attributes.................................................................... 486

3.6.4.10 CD_DSS Clock Domain .................................................................................. 486

3.6.4.10.1 Overview ............................................................................................... 486

3.6.4.10.2 Clock Domain Modes................................................................................. 486

3.6.4.10.3 Clock Domain Dependency ......................................................................... 487

3.6.4.10.4 Clock Domain Module Attributes.................................................................... 488

3.6.4.11 CD_L4_CFG Clock Domain.............................................................................. 488

3.6.4.11.1 Overview ............................................................................................... 488

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