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EE247 Analysis and design of analog-to-digital interface integta...
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Berkeley EECS247 Analysis and design of analog-to-digital interface integtated circuit 2007 Fall
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EECS 247 Lecture 1: Introduction © 2007 H.K. Page 1
EECS 247
Analog-Digital Interface
Integrated Circuits
© 2007
Instructor: Haideh Khorramabadi
UC Berkeley
Department of Electrical Engineering and
Computer Sciences
Lecture 1: Introduction
EECS 247 Lecture 1: Introduction © 2007 H.K. Page 2
Instructor’s Technical Background
• Ph.D., EECS department -UC Berkeley 1985, advisor Prof. P.R. Gray
– Thesis topic: Continuous-time CMOS high-frequency filters
• Industrial background
– 11 years at ATT & Bell Laboratories, N.J., in the R&D area as a circuit designer
• Circuits for wireline communications: CODECs, ISDN, and DSL including
ADCs (nyquist rate & over-sampled), DACs, filters, VCOs
• Circuits intended for wireless applications
• Fiber-optics circuits
– 3 years at Philips Semiconductors, Sunnyvale, CA
• Managed a group in the RF IC department- developed ICs for CDMA &
analog cell phones
– 3 years @ Broadcom Corp. – Director of Analog/RF ICs in San Jose, CA.
• Projects: Gigabit-Ethernet, TV tuners, and DSL circuitry
– Currently consultant for IC design
• Teaching experience
– Has taught/co-taught EE247 @ UCB since 2003
– Instructor for short courses offered by MEAD Electronics
– Adjunct Prof. @ Rutgers Univ., N.J. : Taught a graduate level IC course
EECS 247 Lecture 1: Introduction © 2007 H.K. Page 3
Administrative
• Course web page:
http://inst.eecs.berkeley.edu/~EE247
– Course notes will be uploaded on the course website prior to
each class
– Homeworks & due dates are posted on the course website
– Please visit course website often for announcements
• Lectures are webcast mainly for the benefit of
students @ UCSC
http://webcast.berkeley.edu/courses
– Please try to attend the classes live to benefit from direct
interactions
– Make sure you use the provided microphones when asking
questions or commenting in class
EECS 247 Lecture 1: Introduction © 2007 H.K. Page 4
Office Hours & Grading
• Office hours:
– Tues./Thurs. 2:30-3:30pm @ 563 Cory Hall
(unless otherwise announced in the class)
– Extra office hours by appointment
– Feel free to discuss issues via email:
haidehk@eecs.berkeley.edu
• Course grading:
– Homework/project 50%
– Midterm 20% (tentative date: Oct. 18)
– Final 30%
EECS 247 Lecture 1: Introduction © 2007 H.K. Page 5
Prerequisites & CAD Tools
• Prereqs.
– Basic course in signal processing (Laplace
and z-transform, discrete Fourier
transform) i.e. EE120
– Fundamental circuit concepts i.e. EE105
and EE140
•CAD Tools:
– HSPICE or Spectre
–Matlab
EECS 247 Lecture 1: Introduction © 2007 H.K. Page 6
Analog-Digital Interface Circuitry
Digital
Processor
Analog/Digital
Interface
Analog Input
Analog World
Digital/Analog
Interface
0 0 1
1 1 0
0 1 0
1 0 0 1
1 0 1 0
0 0 1 0
Analog Output
• Naturally occurring signals are analog
• To process signals in the digital domain
∴ Need Analog/Digital & Digital/Analog interface circuitry
Question: Why not process the signal with analog circuits only
& thus eliminate need for A/D & D/A?
EECS 247 Lecture 1: Introduction © 2007 H.K. Page 7
CMOS Technology Evolution versus Time
*Ref: Paul R. Gray UCB EE290 course ‘95
International Technology Roadmap for Semiconductors, http://public.itrs.net
For NMOS @ (V
GS
-V
th
= 0.5V )
75 80 85 90 95 ’00 ’05 ’10
6u
3u
2u
1.5u
1u
0.8u
0.6u
0.35u
0.25u
0.13u
0.1u
1
10
100
f
t
[GHZ]
Year
0.18u
0.065u
0.045u
EECS 247 Lecture 1: Introduction © 2007 H.K. Page 8
CMOS Device Evolution
Progression from 1975 to 2005
• Feature sizes ~X1/100
• Cut-off frequency f
t
~X300
• Minimum size device area ~1/L
2
• Number of interconnect layers ~X8
EECS 247 Lecture 1: Introduction © 2007 H.K. Page 9
Impact of CMOS Scaling on
Digital Signal Processing
Direct beneficiary of VLSI technology down scaling
– Digital circuits deal with “0” & “1” signal levels only
Æ Not sensitive to “analog” noise
– Si Area/function reduced drastically due to
• Shrinking of feature sizes
• Multi metal levels for interconnections (currently >8 metal
level v.s. only 1 in the 1970s)
– Enhanced functionality & flexibility
– Amenable to automated design & test
– “Arbitrary” precision
– Provides inexpensive storage capability
EECS 247 Lecture 1: Introduction © 2007 H.K. Page 10
Analog Signal Processing Characteristics
• Sensitive to “analog” noise
• Has not fully benefited from technology down scaling:
– Supply voltages scale down accordingly
Æ Reduced voltage swings Æ more challenging analog
design
– Reduced voltage swings requires lowering of the
circuit noise to keep a constant dynamic range
Æ Higher power dissipation and chip area
• Not amenable to automated design
• Extra precision comes at a high price
• Rapid progress in DSP has imposed higher demands
on analog/digital interface circuitry
ÆPlenty of room for innovations!
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