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SerDes DFE 16Gbps
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DFE Serdes 16Gbps documentation and design
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350 • 2011 IEEE International Solid-State Circuits Conference
ISSCC 2011 / SESSION 20 / HIGH-SPEED TRANSCEIVERS & BUILDING BLOCKS / 20.3
20.3 Analog-DFE-Based 16Gb/s SerDes in 40nm CMOS
That Operates Across 34dB Loss Channels at Nyquist
with a Baud Rate CDR and 1.2V
pp
Voltage-Mode
Driver
Andrew K. Joy
1
, Hugh Mair
2
, Hae-Chang Lee
3
, Arnold Feldman
3
,
Clemenz Portmann
3
, Neil Bulman
1
, Eugenia Cordero Crespo
1
,
Peter Hearne
1
, Patty Huang
3
, Ben Kerr
1
, Pulkit Khandelwal
1
,
Franz Kuhlmann
2
, Shaun Lytollis
1
, Joaquim Machado
1
,
Casey Morrison
2
, Scott Morrison
2
, Shahriar Rabii
3
,
Dushmantha Rajapaksha
1
, Vishnu Ravinuthula
2
, Giuseppe Surace
1
1
Texas Instruments, Northampton, United Kingdom,
2
Texas Instruments, Dallas, TX,
3
Arda Technologies, Mountain View, CA
In networking systems today data rates are increasing beyond 15Gb/s and yet
the installed backplanes are made of low cost materials with losses in excess of
30dB at 7.5GHz. Standards, such as IEEE802.3ap-10GBASE-KR and OIF-
CEI25G, are specifying SerDes requirements for channels with 25dB loss at
Nyquist and this has driven the development of SerDes with 4 or 5 tap DFEs [1].
Until now, solutions for 34dB or more channel loss have been limited to
10.3Gb/s or below [2,3], whereas this paper describes an adaptive 14-tap DFE
that achieves a 10
-17
BER across a 34dB loss channel at 16Gb/s for a power of
235mW/lane. A baud-rate CDR technique is specifically developed that gives
excellent locking characteristics and alignment for use with a speculative DFE
together with an enhanced swing TX voltage mode driver.
A block diagram of the complete transceiver is shown in Fig. 20.3.1. The trans-
mitter utilizes an enhanced voltage mode driver as shown in Fig. 20.3.2. A stan-
dard voltage mode driver is commonly used in SerDes because of its higher
power efficiency than a CML driver but has the problem of a limited output swing
due to the series termination. This type of driver is normally limited to a maxi-
mum swing of ~800mV
pp
differential [4]. The addition of the CML type pull-up
PMOS devices allows the common mode to be driven by the series driving stage
but the swing to be increased to ~1200mV
pp
differential. This improves the out-
put swing significantly at the cost of a small degradation of approximately 1dB
in the TX output differential return loss.
The TX driver is made up of many slices of output stage that enables the design
to have a 3-tap FIR filter to provide 1 pre-cursor and 1 post-cursor of de-empha-
sis. The pre-cursor can be up to ±17.5% and the post cursor ±37.5% in 2.5%
steps. This has a high pass characteristic that compensates for some of the
channel loss. The number of FIR taps is chosen to allow interoperability with
other SerDes developed using the 10GBASE-KR and FC-16 standards. The
increased swing capability makes the use of higher TX FIR pre- and post-cursor
settings more feasible as these de-emphasize the overall output swing but allow
the main cursor to remain higher.
The receiver utilizes an analog equalizer followed by a 2-stage VGA and a sum-
mer block to add in the DFE correction terms. The samplers are effectively mul-
tiple interleaved 3-bit ADCs with levels adapted to carry out 2-tap DFE specula-
tion and error term slicing for DFE adaption and CDR adaption. This optimization
of the slicing levels reduces the quantization noise that usually limits the per-
formance of an ADC based solution.
The received input signal is terminated by an on-chip t-coil to give return loss
that is more than 10dB down up to 10GHz. This is followed by an analog equal-
izer with variable DC attenuation, pole-zero spacing and bandwidth. This gives
up to 14dB of peaking in steps of <0.5dB and is followed by two VGAs each with
up to 7dB of gain to recover the amplitude of the data. The VGA gain is controlled
by a 7b DAC and is adapted to match the output signal with the linear range of
the following summers.
The samplers are run at one quarter of the incoming data rate and so the sum-
mers are interleaved and have to settle within 4UI. The CDR sampling point uses
a Muller-Mueller baud rate technique but unlike other solutions [5] where h
-1
is
forced to 0 this CDR uses h
0
=h
1
for long reach applications. This has the advan-
tage that the error slicing points fold over for a two-tap speculative DFE as
shown in Fig. 20.3.3 and makes the slicing levels form an interleaved ADC. A fur-
ther advantage is that the h
-1
term is suppressed by locking earlier than the peak
in the symbol response. This does result in higher values for subsequent taps
but this is not a problem as the DFE has a sufficient number of taps to cancel
these. This locking criterion of the CDR is to the zero crossing points similar to
Alexander phase detectors which have a high gain around the lock point and this
results in low CDR jitter. However, with an analog summing and speculative DFE
this also gives the optimum sampling point within the eye.
For shorter reach applications the locking point can be alternatively programmed
to be related to the h
0,
h
1
and h
2
taps in a similar manner that also exhibits the
same folding of the error terms’ slicing levels.
Two of the taps are speculative and the remaining 12 DFE taps are fed back to
the summer with DAC current mirrors. The use of two taps of speculation allows
the feedback loop to the slicer inputs 3UI to settle.
Hardware sequencing controls the front end auto-zeroing, slicer auto-zeroing
and then performs a directed search for the region of operation where sufficient
performance is achieved to give a sufficiently low BER for the CDR and DFE to
lock. The RX is then released to adapt to the optimum CDR, DFE and AEQ set-
tings.
The DFE adaptation uses a sign-sign LMS algorithm from the error slicer out-
puts. The AEQ is separately adapted to maximize the eye height at the cursor
with additional samplers that can also be used for non-destructive eye height
monitoring and plotting of eyes even in an asynchronous environment.
A B8P2 macro consisting of 4 transmit lanes, 4 receive lanes and 2 PLLs, is
1.796×1.195mm
2
in TSMC 40G 40nm CMOS technology. A B8P2 macro is
shown in Fig. 20.3.4. It consumes 235mW per RX/TX pair including PLL over-
head when running at 16Gb/s. The SerDes in silicon operates at 16Gb/s over 24”
of Xcede FR-4 backplane plus evaluation card traces giving a total loss of -34dB.
The transmitter eye is shown at 20Gb/s with a PRBS31 pattern in Fig. 20.3.5. The
TX FIR map of performance of a complete link with a 10
12
bit gate time, togeth-
er with the RX eye plots and bathtub curves for the Xcede backplane trace above
at 16Gb/s are shown in Fig. 20.3.6.
References:
[1] J. F. Bulzacchelli, T. O, Dickson, et al, “A 78mW 11.1Gb/s 5-Tap DFE Receiver
with Digitally Calibrated Current-Integrating Summers in 65nm CMOS,”
ISSCC
Dig. Tech. Papers
, pp.368-369, Feb. 2009.
[2] K. Fukuda, H. Yamashita, et al, “An 8Gb/s Transceiver with 3×-Oversampling
2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane,”
ISSCC Dig.
Tech. Papers
, pp. 98-99, Feb. 2008.
[3] Y. Hidaka, W. Gai, et al, “A 4-Channel 10.3Gb/s Backplane Transceiver Macro
with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,”
ISSCC Dig.
Tech. Papers
, pp.188-189, Feb. 2009.
[4] W. Dettloff, J. C. Eble, et al, “A 32mW 7.4Gb/s Protocol Agile Source-Series
Terminated Transmitter in 45nm CMOS SOI,”
ISSCC Dig. Tech. Papers
, pp. 370-
371, Feb. 2010.
[5] M. Harwood, N.Warke, et al, “A 12.5Gb/s Serdes in 65nm CMOS Using a
Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery,”
ISSCC
Dig. Tech. Papers
, pp. 436-437, Feb. 2007.
978-1-61284-302-5/11/$26.00 ©2011 IEEE
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