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Solutions
1
Solutions for CMOS VLSI Design 4th Edition. Last updated 12 May 2010.
Chapter 1
1.1 Starting with 100,000,000 transistors in 2004 and doubling every 26 months for 12
years gives transistors.
1.3 Let your imagination soar!
1.5
1.7
10
8
2
12 12⋅
26
----------------
⎝⎠
⎛⎞
• 4.6B≈
A
B
C
D
Y
AY
(a)
A
B
Y
(b)
A
B
Y
(c)
(d)
A
C
B
Y
SOLUTIONS
2
1.9
1.11 The minimum area is 5 tracks by 5 tracks (40 λ x 40 λ = 1600 λ
2
).
1.13
1.15 This latch is nearly identical save that the inverter and transmission gate feedback
A0A0A1A1
Y0
Y1
Y2
Y3
(a)
Y1
Y0
A0
A1
A1
A0
A2
(b)
n+n+
p substrate
p+p+
n well
A
Y
VDD
n+
GND
B
CHAPTER 2 SOLUTIONS
3
has been replaced by a tristate feedaback gate.
1.17
(c) 5 x 6 tracks = 40 λ x 48 λ = 1920 λ
2
. (with a bit of care)
(d-e) The layout should be similar to the stick diagram.
1.19 20 transistors, vs. 10 in 1.16(a).
1.21 The Electric lab solutions are available to instructors on the web. The Cadence labs
include walking you through the steps.
Chapter 2
YD
CLK
CLK
CLK
CLK
(b)
AB
C
A
VDD
GND
BC
F
D
A
BC
D
(a)
D
F
A
Y
B
A
C
B
C
SOLUTIONS
4
2.1
2.3 The body effect does not change (a) because V
sb
= 0. The body effect raises the
threshold of the top transistor in (b) because V
sb
> 0. This lowers the current
through the series transistors, so I
DS1
> I
DS2
.
2.5 The minimum size diffusion contact is 4 x 5 λ, or 1.2 x 1.5 μm. The area is 1.8 μm
2
and perimeter is 5.4 μm. Hence the total capacitance is
At a drain voltage of VDD, the capacitance reduces to
2.7 The new threshold voltage is found as
The threshold increases by 0.96 V.
()
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
WWW
CAV
LLL
βμ μ
−
−
⎛⎞
•⋅
⎛⎞
== =
⎜⎟
⎜⎟
⋅
⎝⎠
⎝⎠
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
ds
(mA)
V
gs
= 5
V
gs
= 4
V
gs
= 3
V
gs
= 2
V
gs
= 1
C
db
0V() 1.8()0.42()5.4()0.33()+ 2.54fF==
C
db
5V() 1.8()0.42()1
5
0.98
----------+
⎝⎠
⎛⎞
0.44–
5.4()0.33()1
5
0.98
----------+
⎝⎠
⎛⎞
0.12–
+ 1.78fF==
φ
γ
s
V=
•
•
=
=
•
••
−
−
2 0 026
210
145 10
085
100 10
39 885 10
17
10
8
14
(. )ln
.
.
..
2216 10 117 885 10 2 10 075
07
19 14 17 1 2
... .
.
/
•
()
••
()
•
()
=
=+ +
−−
V
V
ts
γφ
44166−
()
=
φ
s
V.
CHAPTER 3 SOLUTIONS
5
2.9 The threshold is increased by applying a negative body voltage so V
sb
> 0.
2.11 The nMOS will be OFF and will see V
ds
= V
DD
, so its leakage is
2.13 Assume V
DD
= 1.8 V. For a single transistor with n = 1.4,
For two transistors in series, the intermediate voltage x and leakage current are
found as:
In summary, accounting for DIBL leads to more overall leakage in both cases.
However, the leakage through series transistors is much less than half of that
through a single transistor because the bottom transistor sees a small Vds and much
less DIBL. This is called the stack effect.
For n = 1.0, the leakage currents through a single transistor and pair of transistors
are 13.5 pA and 0.9 pA, respectively.
2.15 V
IL
= 0.3; V
IH
= 1.05; V
OL
= 0.15; V
OH
= 1.2; NM
H
= 0.15; NM
L
= 0.15
2.17 Either take the grungy derivative for the unity gain point or solve numerically for
V
IL
= 0.46 V, V
IH
= 0.54 V, V
OL
= 0.04 V, V
OH
= 0.96 V, NM
H
= NM
L
= 0.42 V.
2.19 Take derivatives or solve numerically for the unity gain points: V
IL
= 0.43 V, V
IH
=
0.50 V, V
OL
= 0.04 V, V
OH
= 0.97 V, NM
H
= 0.39, NM
L
= 0.47 V.
2.21 (a) 0; (b) 0.6; (c) 0.8; (d) 0.8
Chapter 3
3.1 First, the cost per wafer for each step and scan. 248nm – number of wafers for four
II vee pA
leak dsn T
V
nv
t
T
== =
−
β
218
69
.
21.8
499
tDD
T
VV
nv
leak dsn T
I
Ivee pA
η
β
−+
== =
(
)
()
21.8 21.8
1
1
69 mV; 69 pA
DD t
t
TT T
DD t
t
TT T
VxVx
Vx
x
nv v nv
leak T T
VxVx
Vx
x
nv v nv
leak
I vee e vee
eee
xI
η
η
η
η
ββ
−
−−
−+
−
−−−
−+
−
⎛⎞
=−=
⎜⎟
⎜⎟
⎝⎠
⎛⎞
−=
⎜⎟
⎜⎟
⎝⎠
==
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