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QorIQ LS1046A Reference Manual
Supports LS1026A
Document Number: LS1046ARM
Rev. 2, 11/2018
QorIQ LS1046A Reference Manual, Rev. 2, 11/2018
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Overview
1.1 Introduction...................................................................................................................................................................125
1.2 Features summary......................................................................................................................................................... 126
1.3 Application examples....................................................................................................................................................127
1.3.1 Multi-service branch office router............................................................................................................... 127
1.3.2 Security appliance / UTM application......................................................................................................... 128
1.3.3 Single board computer................................................................................................................................. 129
1.3.4 SOHO Gateway............................................................................................................................................130
1.4 Module features ........................................................................................................................................................... 131
1.4.1 Arm Cortex-A72 core features.....................................................................................................................131
1.4.2 Arm CoreLink CCI-400 Cache Coherent Interconnect............................................................................... 133
1.4.3 DDR memory controller.............................................................................................................................. 133
1.4.4 DUART........................................................................................................................................................134
1.4.5 Enhanced direct memory access (eDMA) and direct memory access multiplexer (DMAMUX)............... 134
1.4.6 Enhanced secure digital host controller (eSDHC)....................................................................................... 134
1.4.7 FlexTimer Module (FTM)........................................................................................................................... 135
1.4.8 High-speed peripheral interface complex (HSSI)........................................................................................136
1.4.8.1 PCI express.............................................................................................................................. 136
1.4.8.2 SGMII ..................................................................................................................................... 136
1.4.8.3 Queue direct memory access (QDMA)....................................................................................136
1.4.8.4 Serial advanced technology attachment (SATA) controller.................................................... 137
1.4.9 Integrated flash controller (IFC).................................................................................................................. 137
1.4.9.1 IFC NAND flash controller features........................................................................................138
1.4.9.2 NOR flash features...................................................................................................................138
1.4.9.3 General-purpose chip-select machine (GPCM)....................................................................... 138
1.4.10 PreBoot Loader and nonvolatile memory interfaces....................................................................................139
QorIQ LS1046A Reference Manual, Rev. 2, 11/2018
NXP Semiconductors 3
Section number Title Page
1.4.11 Quad serial peripheral interface (QuadSPI).................................................................................................139
1.4.12 System memory management unit MMU-500.............................................................................................139
1.4.13 Serial peripheral interface (SPI)...................................................................................................................140
1.4.14 Universal Serial Bus (USB) 3.0................................................................................................................... 140
1.4.15 Watchdog Timer (WDOG).......................................................................................................................... 141
Chapter 2
Memory Map
2.1 Memory Map Overview................................................................................................................................................143
2.2 Source ID Assignments.................................................................................................................................................143
2.3 Fixed memory map....................................................................................................................................................... 144
2.3.1 DDR Remapping..........................................................................................................................................145
2.4 CCSR Address Map......................................................................................................................................................146
Chapter 3
Signal Descriptions
3.1 Signals Introduction......................................................................................................................................................153
3.2 Signals Overview..........................................................................................................................................................153
3.3 Configuration signals sampled at reset ........................................................................................................................ 180
3.4 Signal multiplexing details........................................................................................................................................... 180
3.4.1 UART, GPIO, FTM, and LPUART signal multiplexing.............................................................................181
3.4.2 ASLEEP and GPIO1 signal multiplexing....................................................................................................182
3.4.3 RTC and GPIO1 signal multiplexing...........................................................................................................182
3.4.4 eSDHC, GPIO2, and GPIO4 signal multiplexing........................................................................................182
3.4.5 PIC and GPIO1 signal multiplexing............................................................................................................ 184
3.4.6 SPI, eSDHC, and GPIO2 signal multiplexing............................................................................................. 185
3.4.7 IFC, QSPI, FTM and GPIO2 signal multiplexing....................................................................................... 186
3.4.8 Ethernet controller 1, FTM1, and GPIO3 signal multiplexing.................................................................... 188
3.4.9 Ethernet controller 2, GPIO3, FTM2, and IEEE1588 signal multiplexing..................................................189
3.4.10 Ethernet management interface1 and GPIO3 signal multiplexing...............................................................190
3.4.11 Ethernet management interface2 and GPIO4 signal multiplexing...............................................................190
QorIQ LS1046A Reference Manual, Rev. 2, 11/2018
4 NXP Semiconductors
Section number Title Page
3.4.12 I2C2, GPIO4, FTM, and eSDHC signal multiplexing.................................................................................191
3.4.13 USB and GPIO4 signal multiplexing...........................................................................................................191
3.5 Output Signal States During Reset............................................................................................................................... 192
Chapter 4
Reset, Clocking, and Initialization
4.1 Reset, clocking, and initialization overview.................................................................................................................193
4.2 External signal descriptions.......................................................................................................................................... 193
4.2.1 System control signals................................................................................................................................. 194
4.2.2 External Clock Signals.................................................................................................................................195
4.3 Clocking Memory Map.................................................................................................................................................196
4.3.1 Core cluster n clock control/status register (Clocking_CLKCCSR)........................................................... 196
4.3.2
Clock generator n hardware accelerator control/status register (Clocking_CLnKCGHWACSR).............. 197
4.3.3
PLL cluster n general status register (Clocking_PLLCnGSR).................................................................... 199
4.3.4 Platform clock domain control/status register (Clocking_CLKPCSR)....................................................... 201
4.3.5 Platform PLL general status register (Clocking_PLLPGSR)...................................................................... 203
4.3.6 DDR PLL general status register (Clocking_PLLDGSR)........................................................................... 205
4.4 Functional description...................................................................................................................................................206
4.4.1 Power-on reset sequence..............................................................................................................................206
4.4.2 Hard reset sequence..................................................................................................................................... 209
4.4.3 Core Soft Reset............................................................................................................................................ 210
4.4.4 RCW State Timing.......................................................................................................................................210
4.4.5 Power-on reset configuration.......................................................................................................................211
4.4.5.1 Reset configuration word (RCW) source.................................................................................212
4.4.5.2 General-purpose input..............................................................................................................213
4.4.5.3 DRAM type select....................................................................................................................213
4.4.5.4 Single Oscillator Source clock select.......................................................................................213
4.4.5.5 IFC external transceiver enable polarity select........................................................................214
4.4.6 Reset configuration word (RCW)................................................................................................................ 214
4.4.6.1 RCW Field Definitions............................................................................................................ 215
QorIQ LS1046A Reference Manual, Rev. 2, 11/2018
NXP Semiconductors 5
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