100GQSFP28SR4光模块数据手册_100G光模块

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AFBR-89CDDZ

QSFP28 Pluggable, Parallel Fiber-Optics Module

100 Gigabit Ethernet Applications

850nm SR4, MMF, MPO Connector

Data Sheet

Description

The Avago Technologies AFBR-89CDDZ is a Four-Channel,

Pluggable, Multi-mode, Fiber-Optic QSFP28 transceiver

for 100 Gigabit Ethernet Applications. This transceiver is

a high performance module for short-range multi-lane

data communication and interconnect applications. It

integrates four data lanes in each direction with each

lane operating at 25.78125 Gbps, giving an aggregated

bandwidth of 103.125 Gbps. It allows optical interoper-

ability up to 100m over an 8- ber (or 12- ber) MPO opti-

cal multi-mode OM4 cable. The push-pull tab facilitates

the insertion and extraction of these transceivers in high

density environment. Each electrical lane operates at

25.78125 Gbps and conforms to the 100GE CAUI4 inter-

face with 802.3 Clause 91 RS-FEC.

Per channel transmitter and receiver retimers, con gured

for 4x25G operation, can be bypassed to enable alterna-

tive data rate transmission.

These modules are designed to operate over multimode

 ber systems using a nominal wavelength of 850nm. The

electrical interface uses a 38 contact QSFP28 edge type

connector. The optical interface uses a conventional 8- -

ber (or 12- ber) MPO connector. This module incorpo-

rates Avago Technologies proven integrated circuit and

VCSEL technology to provide reliable long life, high per-

formance, and consistent service.

Part Number Ordering Options

100 Gigabit Ethernet AFBR-89CDDZ

Evaluation Board* AFBR-89EVB

Evaluation Kit** AFBR-89EVK

* Includes GUI and User Guide

**Includes GUI, User Guide, I2C controller, and power supply

cable

Features

• Compliant to 100GbE electrical and optical

speci cations 802.3bm (Annex 83E CAUI-4 with Clause

91 RS-FEC, Clause 95 100GBASE-SR4)

• 100GbE Link Distances 100m OM4, 70m OM3

• QSFP28 MSA Speci cation Compliant, including new

functions per SFF-8636 Rev 2.4

• Class 1 Eye Safety

• Push-pull tab: ease of transceiver insertion and

extraction

• Operates at 25.78125 Gbps or 10.3125 Gbps per

channel with 64b/66b coded data

• 0 to +70 ºC case temperature operating range

• Proven High Reliability 850 nm technology: Avago

VCSEL transmitter and Avago PIN detector

• Hot pluggable QSFP28 transceiver for ease of

installation and servicing

• Two Wire Serial (TWS) interface with Digital Monitoring

and maskable interrupts for expanded functionality

Applications

• 100 Gigabit Ethernet interconnects

• Datacom/Telecom switch & router connections

• Data aggregation and backplane applications

• Proprietary protocol and density applications

Avago Technologies Con dential

QSFP28 Relevant Speci cations per SFF-8024 (rev 3.3)

Steering

Document

Low Speed, Connector and

Electrical Requirements

Common Management

Spec / Memory Map

Form factor / Module

Mechanical

Cage / Connector Solution

SFF-8665 SFF-8679 SFF-8636 SFF-8661 SFF-8662 and SFF-8663 Style A

SFF-8672 and SFF-8683 Style B

TX EQ & CDRs

4 Channels

Laser Driver

4 Channels

Diagnostic

Monitors

TIA

4 Channels

Control

RX Emph & CDRs

4 Channels

Optical Interface

1×4 VCSEL Array

1×4 PIN Array

Electrical Interface

Din[3:0][p/n] (8)

Dout[3:0][p/n] (8)

SCL

SDA

Mod Sel

LPMode

ModPresL

ResetL

IntL

Figure 1: Transceiver Block Diagram

Transmitter

The optical transmitter portion of the transceiver (see

Figure 1) incorporates a 4-channel VCSEL (Vertical Cav-

ity Surface Emitting Laser) array, a 4-channel Equalization

(EQ) block with integrated CDR and laser driver, diagnos-

tic monitors, control and bias blocks. The transmitter is

designed for IEC-60825 and CDRH eye safety compliance;

Class 1 out of the module. The Tx Input Bu er provides

CML compatible di erential inputs presenting a nominal

di erential input impedance of 100 Ohms. AC coupling

capacitors are located inside the QSFP28 module and are

not required on the host board. For module control and

interrogation, the control interface (LVTTL compatible) in-

corporates a Two Wire Serial (TWS) interface of clock and

data signals. Diagnostic monitors for VCSEL bias, temper-

ature, and power supply voltage are implemented and

results are available through the TWS interface.

Alarm and warning thresholds are established for the

monitored attributes. Flags are set and interrupts gener-

ated when the attributes are outside the thresholds. Flags

are also set and interrupts generated for loss of input sig-

nal (LOS) and transmitter fault conditions. All  ags are

latched and will remain set even if the condition initiating

the latch clears and operation resumes. All interrupts can

Avago Technologies Con dential

be masked and  ags are reset by reading the appropri-

ate  ag register. The optical output will squelch for loss

of input signal unless squelch is disabled. Fault detection

or channel deactivation through the TWS interface will

disable the channel. Status, alarm/warning and fault in-

formation are available via the TWS interface. To reduce

the need for polling, the hardware interrupt signal is pro-

vided to inform hosts of an assertion of alarm, warning,

LOS and/or Tx fault.

Receiver

The optical receiver portion of the transceiver (see Fig-

ure 1) incorporates a 4-channel PIN photodiode array, a

4-channel TIA array, and a 4 channel line driver with in-

tegral CDR, diagnostic monitors, control and bias blocks.

The Rx Output Bu er provides CML compatible di eren-

tial outputs for the high speed electrical interface pre-

senting nominal single-ended output impedances of 100

Ohms di erentially that should be di erentially terminat-

ed with 100 Ohms. AC coupling capacitors are located in-

side the QSFP28 module and are not required on the host

board. Diagnostic monitors for optical input power are

implemented and results are available through the TWS

interface.

Avago Technologies Con dential

Control Signal Interface

The module has the following low speed signals for con-

trol and status: ModSelL, LPMode, ResetL, ModPrsL, IntL.

In addition, there is an industry standard two wire serial

interface scaled for 3.3 volt LVTTL. It is implemented as a

slave device. Signal and timing characteristics are further

de ned in the Control Characteristics and Control Inter-

face & Memory Map sections.

The registers of the serial interface memory are de ned in

the Control Interface & Memory Map section.

Digital Diagnostic Monitoring

The information provides opportunity for predictive fail-

ure identi cation, compliance prediction, fault isolation

and component monitoring.

Predictive Failure Identi cation – The diagnostic infor-

mation allows the host system to identify potential link

problems. Once identi ed, a “failover” technique can be

used to isolate and replace suspect devices before system

uptime is impacted.

Compliance Prediction – The real-time diagnostic pa-

rameters can be monitored to alert the system when op-

erating limits are exceeded and compliance cannot be

ensured. As an example, the real time average receiver

optical power can be used to assess the compliance of the

cable plant and remote transmitter.

Fault Isolation – The diagnostic information can allow

the host to pinpoint the location of a link problem and ac-

celerate system servicing and minimize downtime.

Component Monitoring – As part of host system quali-

 cation and veri cation, real time transceiver diagnostic

information can be combined with system level monitor-

ing to ensure performance and operating environment

are meeting application requirements.

Digital diagnostic monitoring for the following attributes

is implemented.

Transceiver module temperature

Represents the module case temperature (lower page 0

bytes 22-23)

Transceiver module power supply

Reports the module +3.3V supply voltage (lower page 0

bytes 26-27)

Transmitter output power

Reports the average output optical power for each trans-

mitter channel (lower page 0 bytes 50-51 for ch.1, bytes

52-53 for ch.2, bytes 54-55 for ch.3, bytes 56-57 for ch.4)

Transmitter laser bias current

Reports the DC laser bias current for each transmitter

channel (lower page 0 bytes 42-43 for ch.1, bytes 44-45 for

ch.2, bytes 46-47 for ch.3, bytes 48-49 for ch.4)

Receiver input power

Reports the average input optical power for each receiver

channel (lower page 0 bytes 34-35 for ch.1, bytes 36-37 for

ch.2, bytes 38-39 for ch.3, bytes 40-41 for ch.4)

All diagnostic monitor attributes are two-byte  elds. To

maintain coherency, the host must access these with sin-

gle two-byte read sequences.

For each monitored attribute, alarm and warning thresh-

olds are established. Flags are set and interrupts gener-

ated when the attributes are outside the thresholds. All

 ags are latched and will remain set even if the condition

initiating the  ag clears. A mask bit that can be set to pre-

vent assertion of interrupt for each individual attribute ex-

ists for every monitor  ag. Entries in the mask  elds are

volatile.

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