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intel82574的网卡手册,包含寄存器手册和操作流程,中断说明,bar空间映射等等 The 82574 family (82574L and 82574IT) are single, compact, low power components that offer a fully-integrated Gigabit Ethernet Media Access Control (MAC) and Physical Layer (PHY) port.
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Order Number: 317694-016
April 2009 Revision 2.5
Intel® 82574 GbE Controller Family
Datasheet
Product Features
PCI Express* (PCIe*)
— 64-bit address master support for systems
using more than 4 GB of physical memory
— Programmable host memory receive buffers
(256 bytes to 16 KB)
— Intelligent interrupt generation features to
enhance driver performance
— Descriptor ring management hardware for
transmit and receive software controlled reset
(resets everything except the configuration
space)
— Message Signaled Interrupts (MSI and MSI-X)
— Configurable receive and transmit data FIFO,
programmable in 1 KB increments
MAC
— Flow Control Support compliant with the
802.3X Specification
— VLAN support compliant with the 802.1Q
Specification
— MAC Address filters: perfect match unicast
— filters; multicast hash filtering, broadcast filter
— and promiscuous mode
— Statistics for management and RMOM
— MAC loopback
PHY
— Compliant with the 1 Gb/s IEEE 802.3 802.3u
802.3ab Specifications
— IEEE 802.3ab auto negotiation support
— Full duplex operation at 10/100/1000 Mb/s
— Half duplex at 10/100 Mb/s
— Auto MDI, MDI-X crossover at all speeds
High Performance
— TCP segmentation capability compatible with
Large Send offloading features
— Support up to 256 KB TCP segmentation (TSO
v2)
— Fragmented UDP checksum offload for packet
reassemble
— IPv4 and IPv6 checksum offload support
(receive, transmit, and large send)
— Split header support
— Receive Side Scaling (RSS) with two hardware
receive queues
— 9 KB jumbo frame support
— 40 KB packet buffer size
Manageability
— NC-SI for remote management core
— SMBus advanced pass through interface
Low Power
— Magic Packet* wake-up enable with unique
MAC address
— ACPI register set and power down functionality
supporting D0 andD3 states
— Full wake up support (APM and ACPI 2.0)
— Smart power down at S0 no link and Sx no link
— LAN disable function
Technology
— 9 mm x 9 mm 64-pin QFN package with
Exposed Pad*
— Configurable LED operation for customization
of LED displays
— TimeSync offload compliant with the 802.1as
specification
— Wider operating temperature range; -40 °C to
85 °C (82574IT only)
2
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for
use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
IMPORTANT - PLEASE READ BEFORE INSTALLING OR USING INTEL® PRE-RELEASE PRODUCTS.
Please review the terms at http://www.intel.com/netcomms/prerelease_terms.htm carefully before using any Intel® pre-release product, including any
evaluation, development or reference hardware and/or software product (collectively, “Pre-Release Product”). By using the Pre-Release Product, you
indicate your acceptance of these terms, which constitute the agreement (the “Agreement”) between you and Intel Corporation (“Intel”). In the event
that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details.
This product has not been tested with every possible configuration/setting. Intel is not responsible for the product’s failure in any configuration/setting,
whether tested or untested.
The 82574 GbE Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Hyper-Threading Technology requires a computer system with an Intel
®
Pentium
®
4 processor supporting HT Technology and a HT Technology enabled
chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/
products/ht/Hyperthreading_more.htm for additional information.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-
296-9333.
Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009, Intel Corporation. All Rights Reserved.
3
Datasheet—82574 GbE Controller
Contents
1.0 Introduction............................................................................................................10
1.1 Scope..............................................................................................................10
1.2 Number Conventions .........................................................................................10
1.3 Acronyms.........................................................................................................11
1.4 Reference Documents........................................................................................12
1.5 82574 Architecture Block Diagram.......................................................................13
1.6 System Interface...............................................................................................13
1.7 Features Summary............................................................................................13
1.8 Product Codes...................................................................................................16
2.0 Pin Interface ...........................................................................................................18
2.1 Pin Assignments................................................................................................18
2.2 Pull-Up/Pull-Down Resistors and Strapping Options................................................19
2.3 Signal Type Definition........................................................................................19
2.3.1 PCIe.....................................................................................................19
2.3.2 NVM Port...............................................................................................20
2.3.3 System Management Bus (SMBus) Interface..............................................21
2.3.4 NC-SI and Testability.............................................................................. 21
2.3.5 LEDs ....................................................................................................22
2.3.6 PHY Pins ...............................................................................................22
2.3.7 Miscellaneous Pin ...................................................................................23
2.3.8 Power Supplies and Support Pins..............................................................24
2.4 Package...........................................................................................................25
3.0 Interconnects..........................................................................................................26
3.1 PCIe................................................................................................................26
3.1.1 Architecture, Transaction, and Link Layer Properties ...................................27
3.1.2 General Functionality..............................................................................28
3.1.3 Transaction Layer...................................................................................28
3.1.4 Flow Control ..........................................................................................33
3.1.5 Host I/F ................................................................................................35
3.1.6 Error Events and Error Reporting..............................................................36
3.1.7 Link Layer .............................................................................................39
3.1.8 PHY......................................................................................................40
3.1.9 Performance Monitoring ..........................................................................41
3.2 Ethernet Interface.............................................................................................41
3.2.1 MAC/PHY GMII/MII Interface ...................................................................41
3.2.2 Duplex Operation for Copper PHY/GMII/MII Operation.................................42
3.2.3 Auto-Negotiation & Link Setup Features ....................................................43
3.2.4 Loss of Signal/Link Status Indication.........................................................46
3.2.5 10/100 Mb/s Specific Performance Enhancements.......................................47
3.2.6 Flow Control ..........................................................................................48
3.3 SPI Non-Volatile Memory Interface ......................................................................51
3.3.1 General Overview...................................................................................51
3.3.2 Supported NVM Devices ..........................................................................51
3.3.3 NVM Device Detection.............................................................................52
3.3.4 Device Operation with an External EEPROM................................................53
3.3.5 Device Operation with Flash.....................................................................53
3.3.6 Shadow RAM .........................................................................................53
3.3.7 NVM Clients and Interfaces......................................................................55
3.3.8 NVM Write and Erase Sequence................................................................56
3.4 System Management Bus (SMBus) ......................................................................58
82574 GbE Controller—Datasheet
4
3.5 NC-SI...............................................................................................................58
3.5.1 Interface Specification.............................................................................59
3.5.2 Electrical Characteristics ..........................................................................59
4.0 Initialization ............................................................................................................60
4.1 Introduction......................................................................................................60
4.2 Reset Operation.................................................................................................60
4.3 Power Up..........................................................................................................62
4.3.1 Power-Up Sequence................................................................................62
4.3.2 Timing Diagram......................................................................................70
4.4 Global Reset (PE_RST_N, PCIe In-Band Reset) ......................................................71
4.4.1 Reset Sequence......................................................................................71
4.4.2 Timing Diagram......................................................................................72
4.5 Timing Parameters.............................................................................................74
4.5.1 Timing Requirements ..............................................................................74
4.5.2 MDIO and NVM Semaphore......................................................................74
4.6 Software Initialization Sequence..........................................................................75
4.6.1 Interrupts During Initialization..................................................................76
4.6.2 Global Reset and General Configuration.....................................................76
4.6.3 Link Setup Mechanisms and Control/Status Bit Summary.............................76
4.6.4 Initialization of Statistics..........................................................................78
4.6.5 Receive Initialization ...............................................................................78
4.6.6 Transmit Initialization..............................................................................79
5.0 Power Management and Delivery.............................................................................82
5.1 Assumptions .....................................................................................................82
5.2 Power Consumption ...........................................................................................82
5.3 Power Delivery ..................................................................................................83
5.3.1 The 1.9 V dc Rail ....................................................................................83
5.3.2 The 1.05 V dc Rail ..................................................................................83
5.4 Power Management............................................................................................83
5.4.1 82574 Power States................................................................................83
5.4.2 Auxiliary Power Usage.............................................................................84
5.4.3 Power Limits by Certain Form Factors........................................................85
5.4.4 Power States..........................................................................................85
5.4.5 Timing of Power-State Transitions.............................................................89
5.5 Wake Up ..........................................................................................................92
5.5.1 Advanced Power Management Wake Up.....................................................92
5.5.2 PCIe Power Management Wake Up............................................................93
5.5.3 Wake-Up Packets....................................................................................93
6.0 Non-Volatile Memory (NVM) Map ...........................................................................100
6.1 EEUPDATE ......................................................................................................100
6.2 Basic Configuration Table..................................................................................100
6.2.1 Hardware Accessed Words .....................................................................102
6.2.2 Software Accessed Words ......................................................................113
6.3 Manageability Configuration Words.....................................................................114
6.3.1 SMBus APT Configuration Words.............................................................114
6.3.2 NC-SI Configuration Words ....................................................................116
7.0 Inline Functions.....................................................................................................118
7.1 Packet Reception.............................................................................................118
7.1.1 Packet Address Filtering.........................................................................118
7.1.2 Receive Data Storage............................................................................119
7.1.3 Legacy Receive Descriptor Format...........................................................119
7.1.4 Extended Rx Descriptor .........................................................................122
5
Datasheet—82574 GbE Controller
7.1.5 Packet Split Receive Descriptor .............................................................. 128
7.1.6 Receive Descriptor Fetching................................................................... 131
7.1.7 Receive Descriptor Write Back................................................................ 131
7.1.8 Receive Descriptor Queue Structure........................................................ 132
7.1.9 Receive Interrupts................................................................................ 134
7.1.10 Receive Packet Checksum Offloading ...................................................... 137
7.1.11 Multiple Receive Queues and Receive-Side Scaling (RSS)........................... 139
7.2 Packet Transmission........................................................................................ 145
7.2.1 Transmit Functionality........................................................................... 145
7.2.2 Transmission Flow Using Simplified Legacy Descriptors.............................. 146
7.2.3 Transmission Process Flow Using Extended Descriptors.............................. 146
7.2.4 Transmit Descriptor Ring Structure......................................................... 147
7.2.5 Multiple Transmit Queues ...................................................................... 149
7.2.6 Overview of On-Chip Transmit Modes...................................................... 149
7.2.7 Pipelined Tx Data Read Requests............................................................ 150
7.2.8 Transmit Interrupts .............................................................................. 151
7.2.9 Transmit Data Storage.......................................................................... 151
7.2.10 Transmit Descriptor Formats.................................................................. 152
7.2.11 Extended Data Descriptor Format........................................................... 160
7.3 TCP Segmentation........................................................................................... 164
7.3.1 TCP Segmentation Performance Advantages ............................................ 164
7.3.2 Ethernet Packet Format......................................................................... 164
7.3.3 TCP Segmentation Data Descriptors........................................................ 165
7.3.4 TCP Segmentation Source Data.............................................................. 166
7.3.5 Hardware Performed Updating for Each Frame ......................................... 166
7.3.6 TCP Segmentation Use of Multiple Data Descriptors .................................. 167
7.4 Interrupts ...................................................................................................... 170
7.4.1 Legacy and MSI Interrupt Modes ............................................................ 170
7.4.2 MSI-X Mode......................................................................................... 170
7.4.3 Registers............................................................................................. 171
7.4.4 Interrupt Moderation ............................................................................ 173
7.4.5 Clearing Interrupt Causes...................................................................... 175
7.5 802.1q VLAN Support ...................................................................................... 176
7.5.1 802.1q VLAN Packet Format .................................................................. 176
7.5.2 Transmitting and Receiving 802.1q Packets ............................................. 177
7.5.3 802.1q VLAN Packet Filtering ................................................................. 177
7.6 LED's............................................................................................................. 178
7.7 Time SYNC (IEEE1588 and 802.1AS) ................................................................. 179
7.7.1 Overview ............................................................................................ 179
7.7.2 Flow and Hardware/Software Responsibilities ........................................... 180
7.7.3 Hardware Time Sync Elements............................................................... 182
7.7.4 PTP Packet Structure ............................................................................ 185
8.0 System Manageability............................................................................................ 188
8.1 Scope............................................................................................................ 188
8.2 Pass-Through (PT) Functionality........................................................................ 188
8.3 Components of a Sideband Interface.................................................................. 189
8.4 SMBus Pass-Through Interface.......................................................................... 189
8.4.1 General............................................................................................... 190
8.4.2 Pass-Through Capabilities...................................................................... 190
8.4.3 Manageability Receive Filtering............................................................... 191
8.4.4 SMBus Transactions.............................................................................. 198
8.4.5 SMBus Notification Methods................................................................... 202
8.5 Receive TCO Flow............................................................................................ 205
8.6 Transmit TCO Flow .......................................................................................... 205
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