Physical-Design-Complete.pdf_PhysicalDesignInterviewQuestions

Physical-Design-

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Physical Design Concepts

Contents

1. Inputs and outputs of Physical Design

2. Checks and care about before starting the Design

3. Floorplanning

4. Power planning

5. Placement

6. Clocktree synthesis - CTS

7. Clocktree Optimization - CTO

8. Routing

9. Design Rule check - DRC

10. LVS

11. Parasitic Extraction

12. Power Analysis

13. Crosstalk Analysis

14.

Electron Migration

15. Timing Analysis

16. Chip Finishing (DFM or DFY)

17. Low-power Techniques

18. Designs Executed (Projects)

19. Multi-Voltage Design

20. Physical Design objective type questions and answers

21. ASIC Design check list

22. Companies interview questions

Physical Design Concepts

Libraries in Physical Design

Technology libraries are integral part of the ASIC backend EDA tools. Important two libraries are

briefly explained below.

Technology File Libraries

Technology file defines basic characteristic of cell library pertaining to a particular technology

node. They are units used in the design, graphical characteristics like colors, stipple patterns, line

styles, physical parameters of metal layers, coupling capacitances, capacitance models, dielectric

values, device characteristics, design rules. These specifications are divided into technology file

sections.

Units for power, voltage, current etc are defined in technology section.

The color section defines primary and display colors that a tool uses to display designs in the

library. Stipple pattern are defined in stipple sections. Different layer definitions like its current

density, width etc are defined in layer section. Fringe capacitances generated by crossing of

interconnects are defined in fringe cap section.

Similarly several other specifications like metal density, design rules that apply to design in

library, place and route (P&R) rules, slot rule, resistance model are defined in their respective

sections.

Standard Cell Libraries, I/O Cell Libraries, Special Cell Libraries

A standard cell library is a collection of pre designed layout of basic logic gates like inverters,

buffers, ANDs, ORs, NANDs etc.

All the cells in the library have same standard height and have varied width. These standard cell

libraries are known as reference libraries in Astro.

These reference libraries are technology specific and are generally provided by ASIC vendor like

TSMC, Artisan, IBM etc. Standard cell height for 130 TSMC process is 3.65 µM.

In addition to standard cell libraries, reference libraries contain I/O and Power/Ground pad cell

libraries. It also contain IP libraries for reusable IP like RAMs, ROMs and other pre-designed,

standard, complex blocks.

The TSMC universal I/O libraries include several power/ground cells that supply different

voltages to the core, pre-drivers and post drivers. Internal pull-up or pull-down is provided to

some cells in I/O libraries.

Physical Design Concepts

2. Checks and Care About Before Starting the Design

The goal of the HandOff environment is to provide early checking capabilities to ensure that once

the design is routed and has converged in timing on the optimization environments, the SignOff

of the design will produce no surprises. Among surprises that are safeguarded by the HandOff

environment are:

- Naming issues among the different SignOff environments tools: extraction, DRC, LVS.

- LVS issues with respect to power/ground proper definition.- Bad clock implementation

planning.

In case latency are not budgeted properly, it is common to ends-up re implementing the design

from scratch with updated latency/clock definitions.If lucky, it’s only a matter of redoing CTS

and all the routing phase.

In the worst condition, the design is hacked with ECOs on the clock trees to fix timing using large

skews with potential silicon failure.

- Bad optimization through constraints checking. Same consequence as above if not done

properly.

- Bad interpretation of High Fanout nets requirements.

Note:

Failure to budget high fan-out nets(HFN) and clocks can cause full placement re-spin

because of incorrect pre-cts optimization.

In this flow the following information are obtained by the users and validated:

•Inter clock relation ship of the clocks must be aligned together

•Basic checking of constraints in the Zero WLM

• defines all clock roots

• defines all high fanout nets

• budgets all clock latencies and insertion delays of high fanout nets(HFN). The min insertion

delay must be equal to the max insertion delay (known problem).

• if a scan chain description is available, user validate that the budgeted latencies does not cause

too large skews on the scan chains

• user validate that all “create_clocks” have an equivalent clock root in , user validate that all high

fanout nets are defined

• user export pre-cts clock latencies.

•In Unix, user updates the uncertainty definitions of pre/post cts files.

•It is recommended

Note:

Physical Design Concepts

Failure to budget high-fanout nets and clocks can cause full placement re-spin because of

incorrect pre-cts optimization.

Multi Voltage design

Definition: A multi voltage design is a hierarchical design with some blocks being supplied with

a different voltage than the top level. The flow today only support a single voltage per place and

route partitions, but by combining the partitions together, to have indeed multiple configuration.

Check:

As buffers are connected to the periphery of the circuit, it is a good design practice to put them at

the top level.

A net with more than one driver is reported.

A driver is an input top port or an output pin.

A top level port of a block cannot be left unconnected

A top level port of a top design pad cell cannot be left unconnected.

A pass output of a cell having a input pad must be connected only with cells of celltype interface.

Every unbuffered package (with a pass output) pad input must be buffered (of celltype interface).

ClockTree Check:

Vth Consistency:

The clock tree must use cells from the allowed Vth list. Today, that list of Vth correspond to all

Vths available and there is no limitation set.

The clock tree must be using the same Vth or oxide thickness. The check report only the first

instance with a different Vth. This is to ensure different branches of the clock are seeing the same

variation with respect to average power supply, temperature, process.

Max Drive:

It is not allowed to have cells which have a too large drive. There is 2 reasons for this. First

reason is to limit electromigration risks. Second reason is to limit the configuration with large

miller capacitances.

It is not allowed to have cells that are too weak. This is to limit the amount of variations.

It is not allowed to have delay cells in the clock tree. Delay cells have very particular layout and

there is a risk of large pulses being filtered by the delay cell.

It is not allowed to have a too long string of cells with a fanout of 1. If this is the case, it is

possible that the CTS engine compensated wire delays with cells delays. In such case, you can

activate cross corner signoff to ensure signoff is still valid and ignore the error.

difference in cell depth between two branches of the clocktree

It is not allowed to have a very long clock tree branch and a very short one in the same clock

tree, or between different clock roots. This error is reported for branch belonging to the same

clock root. If this is the case, the skew computed during delay calculation or timing analysis is not

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