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HX8367规格书 datasheet TFTdriver
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240x320液晶显示驱动器HX8367规格书 HX8367-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver
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DATA SHEET
( DOC
No. HX8367
-
A
-
DS )
HX8367-A
240RGB x 320 dot, 262K color,
with internal GRAM,
TFT Mobile Single Chip Driver
Version 01 Januaryr, 2011
-P.2-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
January, 2011
1.
General Description ............................................................................................................................... 10
2.
Features................................................................................................................................................... 11
3.
Block Diagram ........................................................................................................................................ 13
4.
Pin Description ....................................................................................................................................... 14
4.1
Pin description ............................................................................................................................... 14
4.2
Pin assignment .............................................................................................................................. 16
4.3
PAD coordinates............................................................................................................................ 17
4.4
Alignment mark.............................................................................................................................. 23
4.5
Bump size...................................................................................................................................... 24
5.
Interface................................................................................................................................................... 25
5.1
System interface circuit ................................................................................................................. 26
5.1.1
Parallel bus system interface................................................................................................ 27
5.1.2
MCU data color coding......................................................................................................... 29
5.1.3
Serial bus system interface .................................................................................................. 43
5.2
RGB interface ................................................................................................................................ 46
5.2.1
Color order on RGB interface............................................................................................... 50
5.2.2
RGB data color coding ......................................................................................................... 51
6.
Display Data GRAM................................................................................................................................ 54
6.1
Display data GRAM mapping ........................................................................................................ 54
6.2
Address counter (AC) of GRAM .................................................................................................... 55
6.2.1
System interface to GRAM write direction............................................................................ 56
6.3
GRAM to display address mapping............................................................................................... 61
6.3.1
Normal display on or partial mode on, vertical scroll off....................................................... 63
6.3.2
Vertical scroll display mode .................................................................................................. 65
6.3.3
Updating order on display active area in RGB interface mode ............................................ 68
7.
Functional Description .......................................................................................................................... 71
7.1
Internal oscillator ........................................................................................................................... 71
7.2
Gamma characteristic correction function ..................................................................................... 72
7.2.1
Gray voltage generator for source driver.............................................................................. 73
7.2.2
Gray voltage generator for digital gamma correction ........................................................... 93
7.3
Tearing effect output line ............................................................................................................... 94
7.3.1
Tearing effect line modes...................................................................................................... 94
7.3.2
Tearing effect line timing....................................................................................................... 96
7.3.3
Example 1: MPU write is faster than panel read .................................................................. 97
7.3.4
Example 2: MPU write is slower than panel read................................................................. 98
7.4
Scan mode setting......................................................................................................................... 99
7.5
LCD power generation circuit ...................................................................................................... 100
7.5.1
Power supply circuit............................................................................................................ 100
7.5.2
LCD power generation scheme.......................................................................................... 102
7.6
Power on/off sequence................................................................................................................ 103
7.7
Input/output pin state ................................................................................................................... 107
7.7.1
Output pins ......................................................................................................................... 107
7.7.2
Input pins ............................................................................................................................ 107
8.
Command.............................................................................................................................................. 108
8.1
Command set .............................................................................................................................. 109
8.2
Index register................................................................................................................................114
8.3
Himax ID register (PAGE0 -R00h)................................................................................................114
8.4
Display mode control register (PAGE0 -01h) ...............................................................................114
8.5
Column address start register (PAGE0 -02~03h).........................................................................115
8.6
Column address end register (PAGE0 -04~05h)..........................................................................115
8.7
Row address start register (PAGE0 -06~07h) ..............................................................................116
8.8
Row address end register (PAGE0 -08~09h)...............................................................................116
8.9
Partial Area Start Row Register (PAGE0 -0A~0Bh)......................................................................117
8.10
Partial Area End Row Register (PAGE0 -0C~0Dh) ......................................................................117
HX8367-A
240RGB x 320 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
January, 2011
-P.3-
Himax Confidential
January, 2011
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
8.11
Vertical scroll top fixed area register (PAGE0 -0E~0Fh) ..............................................................119
8.12
Vertical scroll height area register (PAGE0 -10~11h)...................................................................119
8.13
Vertical scroll button fixed area register (PAGE0 -12~13h)..........................................................119
8.14
Vertical scroll start address register (PAGE0 -14~15h)............................................................... 120
8.15
Memory access control register (PAGE0 -16h) ........................................................................... 122
8.16
COLMOD control register (PAGE0 -17h)..................................................................................... 122
8.17
OSC control register (PAGE0 -18h & R19h) ............................................................................... 124
8.18
Power control 1 register (PAGE0 -1Ah)....................................................................................... 125
8.19
Power control 2 register (PAGE0 -1Bh)....................................................................................... 126
8.20
Power control 3 register (PAGE0 -1Ch)....................................................................................... 127
8.21
Power control 4~5 register (PAGE0 -1Dh~1Eh).......................................................................... 128
8.22
Power control 6 register (PAGE0 -1Fh)....................................................................................... 129
8.23
Power control 7 register (PAGE0 -20h) ....................................................................................... 130
8.24
Read data register (PAGE0 -22h)................................................................................................ 131
8.25
VCOM control 1~3 register (PAGE0 -23~25h) ............................................................................ 132
8.26
Display control 1 register (PAGE0 -26h~R28h)........................................................................... 134
8.27
Frame control register (PAGE0 -29h~R2Ch)............................................................................... 137
8.28
Cycle control register (PAGE0 -2Dh~R2Eh)................................................................................ 139
8.29
Display inversion register (PAGE0 -2Fh)..................................................................................... 140
8.30
RGB interface control register (PAGE0 -31h~R34h)................................................................... 141
8.31
Panel characteristic control register (PAGE0 -36h)..................................................................... 143
8.32
OTP register (PAGE0 -38h ~ R3Ah, R87h) ................................................................................. 144
8.33
Gamma control 1~35 register (PAGE0 -40h~5Dh)...................................................................... 145
8.34
TE control register (PAGE0 -60h, 84h~85h)................................................................................ 150
8.35
ID register (PAGE0 -61h~63h)..................................................................................................... 151
8.36
PTBA Control 1~2 Register (PAGE0 –REAh~REBh).................................................................. 151
8.37
STBA Control 1~2 Register (PAGE0 –RECh~REDh).................................................................. 152
8.38
OTPS1B Register (PAGE0 –RF1h)............................................................................................. 152
8.39
GENON Register (PAGE0 –RF2h).............................................................................................. 152
8.40
Command page select register (RFFh) ....................................................................................... 153
8.41
DGC control register (PAGE1 -00h) ............................................................................................ 154
8.42
DGC LUT register (PAGE1 -01h~63h) ........................................................................................ 154
9.
Layout Recommendation .................................................................................................................... 155
10.
OTP 157
10.1
OTP programming flow................................................................................................................ 157
10.2
OTP table..................................................................................................................................... 158
11.
Electrical Characteristics .................................................................................................................... 160
11.1
Absolute maximum ratings .......................................................................................................... 160
11.2
ESD protection level .................................................................................................................... 160
11.3
DC characteristics ....................................................................................................................... 161
11.3.1
Current consumption .......................................................................................................... 163
11.4
AC characteristics........................................................................................................................ 164
11.4.1
Parallel interface characteristics (8080-series MPU) ......................................................... 164
11.4.2
Serial interface characteristics ........................................................................................... 166
11.4.3
RGB interface characteristics............................................................................................. 167
11.4.4
Reset input timing............................................................................................................... 169
12.
Application Circuit................................................................................................................................ 170
12.1
240RGBx320 MPU application circuit ......................................................................................... 170
12.2
240RGBx320 SPI+RGB application circuit ................................................................................. 171
13.
Ordering Information............................................................................................................................ 172
14.
Revision History ................................................................................................................................... 172
HX8367-A
240RGB x 320 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
January, 2011
-P.4-
Himax Confidential
January, 2011
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Figure 5.1 Register read/write timing in parallel bus system interface (for I80 series MPU)............ 27
Figure 5.2 GRAM read/write timing in parallel bus system interface (for I80 series MPU)............... 28
Figure 5.3 Example of I80-system 18-bit parallel bus interface........................................................ 31
Figure 5.4 Input data bus and GRAM data mapping in 18-bit bus system interface with 18 bit-data
input (“IM3, IM2, IM1, IM”=”1010” or “1000”) ............................................................................. 31
Figure 5.5 Example of I80 system 16-bit parallel bus interface type I .............................................. 32
Figure 5.6 Example of I80 system 16-bit parallel bus interface type II ............................................. 32
Figure 5.7 Input data bus and GRAM data mapping in 16-bit bus system interface with 12 bit-data
input (R17H=03h and “IM3, IM2, IM1, IM0”=”0000”) ................................................................. 33
Figure 5.8 Input data bus and GRAM data mapping in 16-bit bus system interface with 16 bit-data
input (R17H=05h and “IM3, IM2, IM1, IM0”=”0000”) ................................................................. 33
Figure 5.9 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(12+6)
bit-data input (R17H=06h and “IM3, IM2, IM1, IM0”=”0000”) .................................................... 33
Figure 5.10 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(16+2)
bit-data input (R17H=07h and “IM3, IM2, IM1, IM0”=”0000”) .................................................... 33
Figure 5.11 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(2+16)
bit-data input (R17H=04h and “IM3, IM2, IM1, IM0”=”0000”) .................................................... 34
Figure 5.12 Input data bus and GRAM data mapping in 16-bit bus system interface with 12 bit-data
input (R17H=03h and “IM3, IM2, IM1, IM0”=”0010”) ................................................................. 34
Figure 5.13 Input data bus and GRAM data mapping in 16-bit bus system interface with 16 bit-data
input (R17H=05h and “IM3, IM2, IM1, IM0”=”0010”) ................................................................. 34
Figure 5.14 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(12+6)
bit-data input (R17H=06h and “IM3, IM2, IM1, IM0”=”0010”) .................................................... 34
Figure 5.15 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(16+2)
bit-data input (R17H=07h and “IM3, IM2, IM1, IM0”=”0010”) .................................................... 35
Figure 5.16 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(2+16)
bit-data input (R17H=04h and “IM3, IM2, IM1, IM0”=”0010”) .................................................... 35
Figure 5.17 Example of I80 system 9-bit parallel bus interface type I .............................................. 36
Figure 5.18 Example of I80 system 9-bit parallel bus interface type II ............................................. 36
Figure 5.19 Input data bus and GRAM data mapping in 9-bit bus system interface with 18 bit-data
input (R17H=06h and “IM3, IM2, IM1, IM0”=”1001”) ................................................................. 37
Figure 5.20 Input data bus and GRAM data mapping in 9-bit bus system interface with 18 bit-data
input (R17H=06h and “IM3, IM2, IM1, IM0”=”1011”).................................................................. 37
Figure 5.21 Example of I80-system 8-bit parallel bus interface type I.............................................. 38
Figure 5.22 Example of I80-system 8-bit parallel bus interface type II............................................. 38
Figure 5.23 Input data bus and GRAM data mapping in 8-bit bus system interface with 12 bit-data
input (R17H=03h and“IM3, IM2, IM1, IM0”=”0001”) .................................................................. 39
Figure 5.24 Input data bus and GRAM data mapping in 8-bit bus system interface with 16 bit-data
input (R17H=05h and “IM3, IM2, IM1, IM0”=”0001”) ................................................................. 39
Figure 5.25 Input data bus and GRAM data mapping in 8-bit bus system interface with 18 bit-data
input (R17H=06h and “IM3, IM2, IM1, IM0”=”0001”) ................................................................. 39
Figure 5.26 Input data bus and GRAM data mapping in 8-bit bus system interface with 18(2+8+8)
bit-data input (R17H=07h and “IM3, IM2, IM1, IM0”=”0001”) .................................................... 39
Figure 5.27 Input data bus and GRAM data mapping in 8-bit bus system interface with 12 bit-data
input (R17H=03h and“IM3, IM2, IM1, IM0”=”0011”)................................................................... 40
Figure 5.28 Input data bus and GRAM data mapping in 8-bit bus system interface with 16 bit-data
input (R17H=05h and “IM3, IM2, IM1, IM0”=”0011”).................................................................. 40
Figure 5.29 Input data bus and GRAM data mapping in 8-bit bus system interface with 18 bit-data
input (R17H=06h and “IM3, IM2, IM1, IM0”=”0011”).................................................................. 40
Figure 5.30 Input data bus and GRAM data mapping in 8-bit bus system interface with 18(2+8+8)
bit-data input (R17H=07h and “IM3, IM2, IM1, IM0”=”0011”)..................................................... 40
Figure 5.31 Index register read/write timing in 3-wire serial bus system interface........................... 43
Figure 5.32 Data write timing in 3-wire serial bus system interface.................................................. 44
Figure 5.33 Index register write timing in 4-wire serial bus system interface ................................... 44
Figure 5.34 Data write timing in 4-wire serial bus system interface.................................................. 45
HX8367-A
240RGB x 320 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
January, 2011
-P.5-
Himax Confidential
January, 2011
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Figure 5.35 DOTCLK cycle ............................................................................................................... 46
Figure 5.36 RGB interface circuit input timing diagram .................................................................... 47
Figure 5.37 RGB mode timing diagram ............................................................................................ 48
Figure 5.38 RGB 18-bit/pixel on 6-bit Data width.............................................................................. 51
Figure 5.39 RGB 16-bit/pixel on 16-bit data width ............................................................................ 52
Figure 5.40 RGB 18-bit/pixel on 18-bit data width ............................................................................ 53
Figure 6.1 Image data sending order from host................................................................................ 56
Figure 6.2 Image data writing control................................................................................................ 56
Figure 6.3 Example1 for rotation with MY, MX and MV.................................................................... 59
Figure 6.4 Example2 for rotation with MY, MX and MV.................................................................... 60
Figure 6.5 Partial display when ML= ‘0’ ............................................................................................ 64
Figure 6.6 Partial display when ML= ‘1’ ............................................................................................ 64
Figure 6.7 Vertical scrolling ............................................................................................................... 65
Figure 6.8 Memory map of vertical scrolling 1 .................................................................................. 65
Figure 6.9 Memory map of vertical scrolling 2 .................................................................................. 66
Figure 6.10 Memory map of vertical scrolling 3 ................................................................................ 66
Figure 6.11 Vertical scrolling example............................................................................................... 67
Figure 6.12 Data streaming order in RGB I/F ................................................................................... 68
Figure 6.13 Updating order when MY = ‘0’ and MX = ‘0’ .................................................................. 69
Figure 6.14 Updating order when MY = ‘0’ and MX = ‘1’ .................................................................. 69
Figure 6.15 Updating order when MY = ‘1’ and MX = ‘0’ .................................................................. 70
Figure 6.16 Updating order when MY = ‘1’ and MX = ‘1’ .................................................................. 70
Figure 7.1 HX8367-A internal clock circuit........................................................................................ 71
Figure 7.2 Gamma adjustments different of source driver with digital gamma correction................ 72
Figure 7.3 Grayscale control............................................................................................................. 73
Figure 7.4 Gamma resister stream and gamma reference voltage .................................................. 75
Figure 7.5 Relationship between source output and Vcom .............................................................. 92
Figure 7.6 Relationship between GRAM data and output level (normal white panel REV_Panel=“0”)
................................................................................................................................................... 92
Figure 7.7 Block diagram of digital gamma correction...................................................................... 93
Figure 7.8 TE mode 1 output ............................................................................................................ 94
Figure 7.9 TE delay output................................................................................................................ 94
Figure 7.10 TE mode 2 output .......................................................................................................... 95
Figure 7.11 TE output waveform....................................................................................................... 95
Figure 7.12 Waveform of tearing effect signal .................................................................................. 96
Figure 7.13 Timing of tearing effect signal........................................................................................ 96
Figure 7.14 Timing of MPU write is faster than panel read............................................................... 97
Figure 7.15 Display of MPU write is faster than panel read.............................................................. 97
Figure 7.16 Timing of MPU write is slower than panel read.............................................................. 98
Figure 7.17 Display of MPU write is slower than panel read ............................................................ 98
Figure 7.18 Gate scan mode............................................................................................................. 99
Figure 7.19 Block diagram of HX8367-A power circuit ................................................................... 100
Figure 7.20 LCD power generation scheme ................................................................................... 102
Figure 7.21 Display on/off set flow.................................................................................................. 103
Figure 7.22 Standby mode setting flow........................................................................................... 104
Figure 7.23 Deep standby mode setting flow.................................................................................. 105
Figure 7.24 Power supply setting flow ............................................................................................ 106
Figure 8.1 Index register ..................................................................................................................114
Figure 8.2 Himax ID register (PAGE0 -00h).....................................................................................114
Figure 8.3 Display mode control register (PAGE0 -01h)..................................................................114
Figure 8.4 Column address start register upper byte (PAGE0 -02h)...............................................115
Figure 8.5 Column address start register low byte (PAGE0 -03h)...................................................115
Figure 8.6 Column address end register upper byte (PAGE0 -04h)................................................115
Figure 8.7 Column address end register low byte (PAGE0 -05h)....................................................116
Figure 8.8 Row address start register upper byte (PAGE0 -06h) ....................................................116
HX8367-A
240RGB x 320 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
January, 2011
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