没有合适的资源?快使用搜索试试~ 我知道了~
首页DDR_PHY_Interface_Specification_v5_1.pdf
DDR_PHY_Interface_Specification_v5_1.pdf
5星 · 超过95%的资源 需积分: 50 28 下载量 167 浏览量
更新于2023-03-16
评论 2
收藏 1.4MB PDF 举报
DDR_PHY_Interface_Specification_v5_1.pdf
资源详情
资源评论
资源推荐
DDR PHY Interface, Version 5.1 1 of 163
May 21, 2021 Copyright 1995-2021
Cadence Design Systems, Inc.
DFI
DDRPHYInterface
DFI 5.1 Specification
M
AY 21, 2021
2 of 163 DDR PHY Interface, Version 5.1
Copyright 1995-2021 May 21, 2021
Cadence Design Systems, Inc.
Release Information
Rev # Date Change
1.0 30 Jan 2007 Initial Release
2.0 17 Jul 2007 Modifications/Additions for DDR3 Support
2.0 21 Nov 2007 Additional modifications/additions for DDR3 support. Added read and write leveling.
Changes approved by the Technical Committee for DDR3 support.
2.0 21 Dec 2007 Removed references to data eye training for PHY Evaluation mode, added a gate training-
specific mode signal, corrected references and clarified read training
.
2.0 11 Jan 2008 Modified wording; standardized notations in figures, clarified terminology for read and write
leveling.
2.0 26 Mar 2008 Added timing parameter t
rdlvl_en
and t
wrlvl_en
, signal dfi_rdlvl_edge.
2.1 2 Oct 2008 Added initial LPDDR2 support and corrected minor errors from 2.0 release.
2.1 24 Nov 2008 Added frequency change protocol, signal timing definitions, t
rdlvl_load
and t
wrlvl_load
timing
parameters and adjusted diagrams accordingly.
2.1 30 Jan 2009 Added DFI logo.
2.1 31 Mar 2009 Updated width of dfi_rdlvl_edge, corrected erroneous figures, updated t
rdlvl_en
and t
wrlvl_en
definitions.
2.1 20 May 2009 Added low power control interface, modified leveling request signal description to include
frequency change, added dfi_data_byte_disable signal and t
phy_wrdata
timing parameters.
Added DIMM support to the status interface and updated frequency ratios from an example to
a defined method. Updated frequency ratios information for new proposals, modified default
values and requirements for some training interface signals, incorporated LPDDR2 training
operations changes
2.1 22 Jun 2009 Expanded frequency ratio information to include vectored read data, expanded use of
dfi_init_start, added timing diagrams for 1:4 frequency ratio systems
2.1.1 23 Mar 2010 Added reference to the parity interface to the Overview. Changed dfi_parity_in signal to have
a phase index. Modified description of dfi_freq_ratio signal to make it optional except for
MCs/PHYs that support multiple frequency ratios. Expanded figure 32 into two figures to
represent odd and even timing parameters.
2.1.1 01 Apr 2010 Changed minimum value for t
lp_wakeup
.
2.1.1 20 Apr 2010 Corrected figure 3 timing violation. Corrected erroneous sentence for 2T timing. Corrected
figure 35 t
phy_wrlat
timing. Correct incorrect references to t
phy_wrlat
in frequency ratio read
examples.
2.1.1 27 May 2010 Added Figure 4 and text to explain differences between Figure 3 and 4.
2.1.1 09 Jun 2010 Modified text in dfi_init_start and surrounding figures 3 and 4 for more clarity.
3.0 21 May 2012 Added DDR4 DRAM support for: CRC, CA parity timing, CRC and CA parity errors, DBI,
leveling support, and CA modifications. Added DFI read data rotation clarification, read data
pointer resynchronization, independent timing of DFI read data valid per data slice, data path
chip select, error interface, and programmable parameters. Renamed PHY evaluation mode.
Removed MC evaluation mode and t
phy_wrdelay
timing parameter. Added support for refresh
during training, multiple CS training, enhancements to the update interface and the idle bus
definition
3.1 19 May 2012 Added support for LPDDR3. Enhanced the Low Power Control Interface to have separate
control and data requests. Added the PHY-Requested Training Interface to enable PHY-
independent training in non-DFI training mode.
-- 14 Nov 2013 Synchronized book files to 3.1 in advance of upcoming changes from JM.
DDR PHY Interface, Version 5.1 3 of 163
May 21, 2021 Copyright 1995-2021
Cadence Design Systems, Inc.
-- 21 Nov 2013 Incorporated review corrections.
-- 21 Mar 2014 Incorporated committee comments, corrected erroneous cross references, fine-tuned
formatting, fine-tuned typographical items.
4.0 04 Aug 2017 Merged DFI 4.0 Spec Addendum to DFI 3.1. Added support for LPDDR4, DB training, per-
slice read leveling, DFI read/write chip select, write DQ training, PHY master interface,
frequency indicator, DFI disconnect protocol, DFI data bit disabling, slice parameter,
geardown mode, DFI feature and matrix topology matrix, 3D stack support and inactive CS
support. Also modified CA training, write leveling strobe and changed the DFI training to be
optional. Enhanced DFI read data eye training sequence, update interface for self-refresh exit
20 Jul 2017 Incorporated review changes from 4.0 Addendum merge.
5.0 27 Apr 2018 Corrected formatting, spelling and content errors from 4.0 version
5.1 26 Mar 2021 Incorporated new proposals for DFI 5.1, standardized look and feel of all figures, added new
signals and updated tables as a result.
Proprietary Notice
No part of this document may be copied or reproduced in any form or by any means without prior written consent of
Cadence.
Cadence makes no warranties with respect to this documentation and disclaims any implied warranties of
merchantability or fitness for a particular purpose. Information in this document is subject to change without notice.
Cadence assumes no responsibility for any errors that may appear in this document.
Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any
representations or warranties as to the completeness, accuracy, or usefulness of the information contained in this
document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does
Cadence assume any liability for damages or costs of any kind that may result from use of such information.
© Copyright 2021 Cadence Design Systems, Inc. All rights reserved worldwide. Portions of this material are © JEDEC
Solid State Technology Association. All rights reserved. Reprinted with permission.
RESTRICTED RIGHTS LEGEND
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraphs (c)(1)(ii) of the
Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.
Destination Control Statement
All technical data contained in this product is subject to the export control laws of the United States of America.
Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to
determine the applicable regulations and to comply with them.
Trademarks
Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc.
All other products or brand names mentioned are trademarks or registered trademarks of their respective holders.
End User License Agreement2
1.Subject to the provisions of Clauses 2, 3, 4, 5 and 6, Cadence hereby grants to licensee ("Licensee") a perpetual,
nonexclusive, nontransferable, royalty free, worldwide copyright license to use and copy the DFI (DDR PHY Interface)
specification (the "DFI Specification") for the purpose of developing, having developed, manufacturing, having
manufactured, offering to sell, selling, supplying or otherwise distributing products which comply with the DFI
Specification.
2.THE DFI SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES EXPRESS, IMPLIED OR
STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY,
4 of 163 DDR PHY Interface, Version 5.1
Copyright 1995-2021 May 21, 2021
Cadence Design Systems, Inc.
MERCHANTABILITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE.
3.No license, express, implied or otherwise, is granted to Licensee, under the provisions of Clause 1, to use Cadence's or
any other person or entity participating in the development of the DFI Specification listed herein (individually
"Participant," collectively "Participants") trade name, or trademarks in connection with the DFI Specification or any
products based thereon. Nothing in Clause 1 shall be construed as authority for Licensee to make any representations on
behalf of Cadence or the other Participants in respect of the DFI Specification.
4.NOTWITHSTANDING ANYTHING ELSE WILL CADENCE'S TOTAL AGGREGATE LIABILITY FOR ANY
CLAIM, SUIT, PROCEEDING OR OTHERWISE, RELATING IN ANYWAY TO THE DFI SPECIFICATION
EXCEED $1.00USD.
5.NOTWITHSTANDING ANYTHING ELSE WILL ANY PARTICIPANT'S TOTAL AGGREGATE LIABILITY FOR
ANY CLAIM, SUIT, PROCEEDING OR OTHERWISE, RELATING IN ANYWAY TO THE DFI SPECIFICATION
EXCEED $1.00USD.
6.Licensee agrees that Cadence and the Participants may use, copy, modify, reproduce and distribute any written
comments or suggestions ("Communications") provided regarding the DFI Specification by Licensee and that Licensee
will not claim any proprietary rights in the DFI Specification, or implementations thereof by any Participant or third
party, as a result of the use of the Communications in developing or changing the DFI Specification. Cadence and the
participants will have no confidentiality obligations with respect to the Communications and Licensee will not include
any confidential information of Licensee or any third party in any Communications.
Participants
AMD ARM Broadcom Cadence Intel Samsung ST Synopsys Uniquify
DDR PHY Interface, Version 5.1 5 of 163
May 21, 2021 Copyright 1995-2021
Cadence Design Systems, Inc.
Contents
1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.0 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Optional Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 DFI Feature Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 Global Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.2 Memory Topology-Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.3 DFI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4 Definition of a Slice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.0 Interface Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.1 Mapping the CA Bus to the dfi_address Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.2 Clock Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.3 Frequency Ratio Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.4 CRC and CA Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.5 2N Mode Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Write Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.1 Write Data Mask/Write DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.2 Write Data Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.3 Write Data CRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.4 Frequency Ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.5 Write Data Signals and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Read Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1 Read DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.2 Read Data Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.3 Read Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.4 Frequency Ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
剩余162页未读,继续阅读
Levanhit
- 粉丝: 0
- 资源: 1
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- 2023年中国辣条食品行业创新及消费需求洞察报告.pptx
- 2023年半导体行业20强品牌.pptx
- 2023年全球电力行业评论.pptx
- 2023年全球网络安全现状-劳动力资源和网络运营的全球发展新态势.pptx
- 毕业设计-基于单片机的液体密度检测系统设计.doc
- 家用清扫机器人设计.doc
- 基于VB+数据库SQL的教师信息管理系统设计与实现 计算机专业设计范文模板参考资料.pdf
- 官塘驿林场林防火(资源监管)“空天地人”四位一体监测系统方案.doc
- 基于专利语义表征的技术预见方法及其应用.docx
- 浅谈电子商务的现状及发展趋势学习总结.doc
- 基于单片机的智能仓库温湿度控制系统 (2).pdf
- 基于SSM框架知识产权管理系统 (2).pdf
- 9年终工作总结新年计划PPT模板.pptx
- Hytera海能达CH04L01 说明书.pdf
- 数据中心运维操作标准及流程.pdf
- 报告模板 -成本分析与报告培训之三.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论1