MIPI_D-PHY_Datasheet_Rev-2-0-mipi协议

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DATASHEET

MIPI D-PHY

Arasan Chip Systems, Inc.

2010 North First Street, Suite #510

San Jose, CA 95131

Ph:408-282-1600

Fx:408-282-7800

www.arasan.com

December, 2012

DISCLAIMER

This document is written in good faith with the intent to assist the readers in the use of the product.

Circuit diagrams and other information relating to Arasan Chip Systems’ products are included as a

means of illustrating typical applications. Although the information has been checked and is

believed to be accurate, no responsibility is assumed for inaccuracies. Information contained in this

document is subject to continuous improvements and developments.

Arasan Chip Systems’ products are not designed, intended, authorized or warranted for use in any

life support or other application where product failure could cause or contribute to personal injury

or severe property damage. Any and all such uses without prior written approval of an Officer of

Arasan Chip Systems Inc. will be fully at the risk of the customer.

Arasan Chip Systems Inc. disclaims and excludes any and all warranties, including without

limitation any and all implied warranties of merchantability, fitness for a particular purpose, title,

and infringement and the like, and any and all warranties arising from any course or dealing or

usage of trade.

This document may not be copied, reproduced, or transmitted to others in any manner. Nor may

any use of information in this document be made, except for the specific purposes for which it is

transmitted to the recipient, without the prior written consent of Arasan Chip Systems, Inc. This

specification is subject to change at anytime without notice. Arasan Chip Systems Inc. is not

responsible for any errors contained herein.

In no event shall Arasan Chip Systems Inc. be liable for any direct, indirect, incidental, special,

punitive, or consequential damages; or for lost of data, profits, savings or revenues of any kind;

regardless of the form of action, whether based on contract; tort; negligence of Arasan Chip

Systems or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of

buyers is held to have failed of its essential purpose, and whether or not Arasan Chip Systems Inc.

has been advised of the possibility of such damages.

Restricted Rights

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in

FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

No part of this specification may be reproduced in any form or means, without the prior written

consent of Arasan Chip Systems, Inc.

Questions or comments may be directed to:

Arasan Chip Systems, Inc.

2010 North First Street

Suite 510, San Jose, CA 95131.

Ph: 408-282-1600

Fx: 408-282-7800

Email: sales@arasan.com

http://www.arasan.com

CONTENTS

1 INTRODUCTION ............................................................................................................................ 3

2 FEATURES ..................................................................................................................................... 4

3 ARCHITECTURE ............................................................................................................................. 5

3.1 D-PHY Based Interconnect Architecture ............................................................................... 5

3.2 D-PHY Lane Architecture ....................................................................................................... 6

3.3 Arasan D-PHY Architecture ................................................................................................... 7

4 D-PHY PAD TABLE ......................................................................................................................... 8

5 HARD MACRO DELIVERABLES .................................................................................................... 14

TABLES

Table 1: Function Description of D-PHY Pads for Clock Lane ......................................................... 8

Table 2: Function Description of D-PHY Pads for First Data Lane .................................................. 8

Table 3: Function Description of D-PHY Pads for Second Data Lane .............................................. 8

Table 4: Function Description of D-PHY Pads for Third Data Lane ................................................. 9

Table 5: Function Description of D-PHY Pads for Fourth Data Lane ............................................... 9

Table 6: Function Description of PLL Pads ...................................................................................... 9

Table 7: PPI Pad Table Pin Description ........................................................................................... 9

Table 8: Power Pads ...................................................................................................................... 13

Table 9: Ports for trim_bits ........................................................................................................... 13

FIGURES

Figure 1: MIPI Link Diagram for Four Data Lanes ........................................................................... 5

Figure 2: D-PHY Lane Architecture.................................................................................................. 6

Figure 3: Analog and Digital D-PHY Block Diagram ......................................................................... 7

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