H9TQ64A8GTCCUR数据手册

This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility

for use of circuits described. No patent licenses are implied.

Rev 0.1 / Jul. 2016 1

eMCP Specification

8GB eMMC (x8)

+ 8Gb LPDDR3 (x32)

Rev 0.1 / Jul. 2016 2

H9TQ64A8GTCCUR

8GB eMMC (x8) / LPDDR3 8Gb(x32)

Rev 0.1 / Jul. 2016 3

H9TQ64A8GTCCUR

8GB eMMC (x8) / LPDDR3 8Gb(x32)

● Operation Temperature

- (-25)

● Package

- 221-ball FBGA

- 11.5x13.0mm

report

(Bold features are added in eMMC5.1)

• VDD1 = 1.8V (1.7V to 1.95V)

• VDD2 and VDDQ = 1.2V (1.14V to 1.30)

- two data accesses per clock cycle

• Differential clock inputs (CK_t, CK_c)

• Bi-directional differential data strobe (DQS_t, DQS_c)

- Source synchronous data transaction aligned to bi-direc-

tional differential data strobe (DQS_t, DQS_c)

- Data outputs aligned to the edge of the data strobe

(DQS_t, DQS_c) when READ operation

- Data inputs aligned to the center of the data strobe

(DQS_t, DQS_c) when WRITE operation

• DM masks write data at the both rising and falling edge of

• PASR (Partial Array Self Refresh) by Bank Mask and Segment

• DS (Drive Strength)

• ZQ (Calibration)

• ODT (On Die Termination)

Rev 0.1 / Jul. 2016 4

H9TQ64A8GTCCUR

8GB eMMC (x8) / LPDDR3 8Gb(x32)

Rev 0.1 / Jul. 2016 5

H9TQ64A8GTCCUR

8GB eMMC (x8) / LPDDR3 8Gb(x32)

H9TQ64A8GTBCCUR-KUM

3.3V

1.8V/1.2/1.2/1.2

8GB (x8)

8Gb (x32)

200MHz