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DSP开发板6678原理图
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更新于2023-03-16
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DSP开发板TI TMS320C6678 EVM Board 原理图,节省开发时间
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D D
C C
B B
A A
DSPM-8301E
TI TMS320C6678 EVM Board
Project Code :
PCB Rev. A104-1
PCB PN :
PCB Thickness : 62 mils(1.6mm)
12 Layers
19C2830103
DISCLAIMER: THIS CIRCUIT DESIGN IS
PROVIDED AS REFERENCE ONLY,
WITHOUT WARRANTY EXPRESSED OR
IMPLIED. THE USER IS ENCOURAGED
TO PERFORM ALL DUE DILIGENCE WITH
RESPECT TO DESIGN AND ANALYSIS.
Copyright (C) 2010 Texas Instruments Incorporated.
All rights reserved. This document is proprietary to TI
and is intended solely for use by TI and its customers.
This document is not to be reproduced, distributed, or
disclosed to other parties in its entirety or in part
without the express written consent of TI.
TI Information - Selective
Disclosure
Texas Instruments
20450 Century Blvd
Germantown, MD 20874
USA
1.0 oz
1.0 oz
1.0 oz
1.0 oz
1.0 oz
1.0 oz
TOP
L2_GND
L3
L4_PWR
L5
L6_GND
L7_GND
L8
L9_PWR
L10
L11_GND
BOT
1.0 oz
1.0 oz
0.5 oz
0.5 oz
0.5 oz
0.5 oz
3.6mils
4mils
4.8mils
5mils
4.5mils
4mils
4.5mils
5mils
4.8mils
4mils
3.6mils
p.p
core
core
p.p
p.p
core
p.p
core
core
p.p
p.p
Rev. 3A
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
COVER PAGE
C
1 40Monday, March 12, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
COVER PAGE
C
1 40Monday, March 12, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
COVER PAGE
C
1 40Monday, March 12, 2012
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
COVER PAGE
02
04
03
06
08
07
05
09
10
12
14
13
16
15
11
18
20
19
22
21
17
23
24
25
26
27
28
29
30
01
TITLE & TABLE OF CONTENTS
Page
Description
32
34
33
Description
Page
31
BLOCK DIAGRAM_AMC
POWER SEQUENCE
POWER CONSUMPTION
POWER DISTRIBUTION
CLOCK DIAGRAM
35
Power VCC1V536
37
History_0
Power ucd9222
Power_VCC5 / VCC3V3_AUX
Power_1.2V/1.8V/2.5V/0.75V
FPGA_XC3S200AN_C
FPGA_XC3S200AN_B
DDR3_ECC
DDR3
FPGA_XC3S200AN_A
Connectors for HyperLink & Debug
RJ45/MISC
Gigabit Ethernet PHY
USB-JTAG
CLOCK_GEN3
CLOCK GEN2
DSP_POWERA
DSP_POWERB
DSP_POWERC
DSP_GND
DSP_SERDES_PORTS
DSP_DDR3
DSP_EMIF
DSP_JTAG_EMU_TSIP
DSP_MISC
DSP_CLOCK_Smart Reflex
BUS Management Map
AMC GF
MMC
FPGA_BLOCK
TITLE & TABLE OF CONTENTS
38
39
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
TITLE & TABLE OF CONTENTS
C
2 40Wednesday, March 07, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
TITLE & TABLE OF CONTENTS
C
2 40Wednesday, March 07, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
TITLE & TABLE OF CONTENTS
C
2 40Wednesday, March 07, 2012
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AMC Board
AMC Port mapping
Port mapping
100MHz
SGMII
PIN
12
11
Port mapping
PIN
13
14
15
00
01
02
03
04
05
06
07
08
09
10
16
17
18
19
20
TCLKA
TCLKB
FCLKA
TCLKC
TCLKD
PCI-E_1
PCI-E_2
SRIO_1
SRIO_2
SRIO_3
SRIO_4
TSIP1 [0..3]
Alternate I2C link
TSIP_CLK0
TSIP_CLK1
TSIP_FS0
TSIP_FS1
TSIP0 [0..3]
N25Q128A21BSF40F
TMS320C6678
1
+V3.3_MP
UART
MDIO
MAC1
EMU[2:17]
JTAG&EMU[0:1]
MAC0
PCIEx2
EMIF
I2C
Hyper Link
DDR3
Miscellaneous I/O conn.
GPIO[0:15](1.8V)
EMIF16(1.8V)
DSP_SPI(1.8V)
DSP_UART(3.3V)
DSP_I2C(1.8V)
DSP_UART
MAX3221EAE
RS232
CH-A
CH-B
USB-JTAG
FT2232HL
DSP_SGMII_P1 & MDIO
DSP_UART
USB
Mini-USB
ENET PHY
88E1111-B2
RJ45
SRIOx4
TSIPx2
SGMIIx1
PCIEx2
SRIOx4
GPIO
SPI
MMC
IPMB-L
EMIF
AMC_State
#0
AMC_State
from MMC
DSP
POWER 12V
PWR CONN
DIP SW
GPIO[0:15]
SPI
AT25128B
SPI EEPROM
Power
FPGA
Others
RAM
Power Control
PHY
(MSP430)
DDR3 -1333
DDR3-1333
w/ ECC
128M X 16 / 2GB
DSP_SPI#1
MMC
JTAG
(XILINX)
DSP_GPIO
XC3S200AN
FPGA
CLK_SPI2
CLK_SPI3
ROM_SPI
HyperLink
50Gbps
iPass+HD
DSP
to FPGA
DSP_I2C
TSIPx2
128k-bit
Power Control
Sequence
Control
SPI Flash
NOR 128M-bit
JTAGFPGA JTAG
60-Pin EMU CONN.
EMU[2:17]
JTAG & EMU[0:1]
HyperLink CONN.
JTAG &
EMU[0:1]
2.54mm
COM1 connector
CLK#1
CDCE62005
CDCE62005
CLK#2
DSP_SGMII_P1 & MDIO
BLOCK DIAGRAM_AMC
DIP_SWITCH
SWITCH
(TS3L301)
TSIPx2
Level-Shifter
EMIFA00
EMIFA01
EMIFA02
EMIFA03
EMIFA05
EMIFA04
EMIFA06
EMIFA07
EMIFA08
EMIFA09
EMIFA11
EMIFA10
EMIFA14
EMIFA13
EMIFA12
EMIFA15
EMIFA16
EMIFA17
EMIFA18
EMIFA19
EMIFA20
EMIFA21
EMIFA22
EMIFA23
EMIFD0
EMIFD1
EMIFD2
EMIFD3
EMIFD4
EMIFD5
EMIFD6
EMIFD7
EMIFD8
EMIFD9
EMIFD10
EMIFD11
EMIFD12
EMIFD13
EMIFD14
EMIFD15
EMIFCE1Z
EMIFCE2Z
EMIFBE0z
EMIFBE1z
EMIFOEz
EMIFWEz
EMIFRnW
EMIFWAIT1
40
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO07
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
77
SCL
SDA
GPIO06
TIMI0
TIMI1
SSPMISO
SSPMOSI
UARTTXD
UARTRXD
TIMO1
SSPCS1
SSPCK
UARTCTS
UARTRTS
TIMO0
80 39
Port mapping
PIN
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Port mapping
PIN
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
Port mapping
PIN
01
03
05
07
09
11
13
15
17
19
21
23
25
27
29
31
33
35
37
Port mapping
PIN
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
79
2
80
1
79
GND
GND
Miscellaneous I/O 80 Pin conn. Signal
NU Resistors
DDR3(ECC)
1Gb X 8
EEPROM
M24M01-HRMN6TP
128k-byte
DEBUG_LED
BM_GPIO(0~15) /
PCIESSEN / User define
D2
User controlled LED - 4
SYSPG_D1 LED
D1
LEVEL
SHIFT
SWITCH
(TS3L301)
AMC JTAG
AMC JTAG
JTAG
SBW_MMC1
UCD9222_PMbus
AMC_JTAG
NUMONYX
NAND512R3A2DZA6E
512Mb 64M X8)
NAND FLASH
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
BLOCK DIAGRAM_AMC
C
3 40Wednesday, March 07, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
BLOCK DIAGRAM_AMC
C
3 40Wednesday, March 07, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
BLOCK DIAGRAM_AMC
C
3 40Wednesday, March 07, 2012
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
88E1111
DSP TMS320C6678
CVDD
When power on
When power down
VDD
DSP
TMS320C6678
VCC1V0 Scaled/(CVDD)
VCC1V0 Fixed/(CVDD1)
VCC1V8/ (DVDD18)
VCC3V3_MP
Power Sequence
VCC12
VCC_1V0 scaled
XC3S200AN
VCC2V5
DSP
TMS320C6678
VCC1V8
DDR3
SDRAM
VCC1V0
DSP TMS320C6678
DDR3 Vref
DSP TMS320C6678
DDR3
DDR3
MMC
VCC_1V0 Fixed
VCC1V8
0ms<t<100us
0ms<t<100us
VCC1V8
0ms<t<100us
VCC_1V0 Fixed
0ms<t<100us
VCC_1V0 scaled
VDD
0ms<t<100ms
Ther is no specific power-up nor
power-down sequence.
DSP TMS320C6678
DSP TMS320C6678
1.5V/(DDR3_IO)
0.75V/(DDR3_Vref)
0ms<t<100us
1.5V/(DDR3_IO)
0.75V/(DDR3_Vref)
88E1111 (PHY)
2.5V
88E1111
1.2V
RESET#
T=5mS
RESETFULL#
Reset Sequence
VCC3V3_MP_AMC
S6
S0
S3
S4
S5
S7
S8
S9
S10
88E1111
PMBUS &
UCD9222_ENA2
VCC1V8_EN
VCC1V5_EN
VCC0V75_EN
VCC2V5_EN
FT2232H
Other
S11
S13
S12
S14
S15
S16
T0
S2 plane power stable to S3 enable signal assertion
DescriptionLabel Time
1ms
POR#
T=0mS
VCC3V3_AUX
2.5V/ 1.2V
1.5V/(DDR3_IO)
0.75V/(DDR3_Vref)
VCC5_EN
S17
S18
XDS560V2 Mazzenine Board
VCC5
VCC1V2
XC3S200AN
S2
XILINX_XC3S200AN
1.2V_AUX (VCCINT)
1.8V_AUX (VCC1V8_AUX)
Ther is no specific power-up nor
power-down sequence.
XILINX_XC3S200AN
VCC1V8_AUX
XC3S200AN
S1
by DSP chip
RESETSTAT#
0.75V (DSP)
1.0V_scaled
1.0V_fixed
VCC1V8
1.5V (DSP)
3.3V / 1.8V/
1.2V
REFCLKP&N
DDRCLKP&N
CLK Sequence
3.3V_AUX (VCCAUX)
Power Sequence
VCC0V75
UCD9222_ENA1
VCC1V5
UCD9222_VID2 &
by
REFCLK3_PD#
by
REFCLK2_PD#
CLOCK2_PLL_LOCK
CLOCK3_PLL_LOCK
T=5mS
T=5mS
T=5mS
T=5mS
T=5mS
T=5mS
T=5mS
including
peripherals.
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
Power Sequence
C
4 40Wednesday, March 07, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
Power Sequence
C
4 40Wednesday, March 07, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
Power Sequence
C
4 40Wednesday, March 07, 2012
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
POWER CONSUMPTION
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
POWER CONSUMPTION
C
5 40Wednesday, March 07, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
POWER CONSUMPTION
C
5 40Wednesday, March 07, 2012
Title
Size
Document Number
Rev
Date:
Sheet
of
Designed for TI by ADVANTECH
DSPM-8301E
A104-1
POWER CONSUMPTION
C
5 40Wednesday, March 07, 2012
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