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镁光l95b手册,含有bga272定义
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更新于2023-03-16
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镁光l95b芯片数据手册,内部操作时序等,包含bga152、bga272定义,相当有用。
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NAND Flash Memory - MLC+
MT29F128G08CBCCB, MT29F256G08CECCB, MT29F512G08C[K/M]CCB,
MT29F512G08CLCCB, MT29F1T08CQCCB, MT29F1T08CUCCB,
MT29F2T08CTCCB, MT29F2T08CVCCB
Features
• Open NAND Flash Interface (ONFI) 3.2-compliant
1
• JEDEC NAND Flash Interface Interoperability
(JESD230) compliant
• Multiple-level cell (MLC) technology
• Organization
– Page size x8: 18,256 bytes (16,384 + 1872 bytes)
– Block size: 512 pages (8192K + 936K bytes)
– Plane size: 2 planes x 1048 blocks per plane
– Device size: 128Gb: 2096 blocks;
256Gb: 4192 blocks;
512Gb: 8384 blocks;
1Tb: 16,768 blocks
2Tb: 33,536 blocks
• NV-DDR2 I/O performance
– Up to NV-DDR2 timing mode 6
– Clock rate: 6ns (NV-DDR2)
– Read/write throughput per pin: 333 MT/s
• NV-DDR I/O performance
– Up to NV-DDR timing mode 5
– Clock rate: 10ns (NV-DDR)
– Read/write throughput per pin: 200 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
–
t
RC/
t
WC: 20ns (MIN)
– Read/write throughput per pin: 50 MT/s
• Array performance
– Read page: 115µs (MAX)
– Program page: 1600µs (TYP)
– Erase block: 3ms (TYP)
• Operating Voltage Range
– V
CC
: 2.7–3.6V
– V
CCQ
: 1.7–1.95V
• Command set: ONFI/JEDEC NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read Unique ID
– Copyback
– SLC Mode
2
– Read Retry
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 160)
3
.
• RESET (FFh) required as first command after pow-
er-on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the NV-DDR/NV-
DDR2 interface
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
3
– Data retention: JESD47 compliant; see qualifica-
tion report
– Endurance: 3000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): -40ºC to +85ºC
• Package
– 152-ball BGA
– 272-ball BGA
Notes:
1. The ONFI 3.2 specification is available at
www.onfi.org.
2. Contact factory for technical details regard-
ing SLC mode.
3. Read Retry operations are required to ach-
ieve specified endurance and for general ar-
ray data integrity.
Micron Confidential and Proprietary
MLC 128Gb to 2Tb Async/Sync NAND
Features
PDF: 09005aef8569746c
L95B_pluc_128_256_512Gb_1Tb_2Tb_Async_Sync_NAND.pdf Rev. F 1/19/18 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 128G 08 C B C C B ES :C
Micron Technology
NAND Flash
29F = NAND Flash memory
Density
128G = 128Gb
256G = 256Gb
512G = 512Gb
1T = 1Tb
Device Width
08 = 8 bits
Level
Bit/Cell
C 2-bit
Classification
Die # of CE# # of R/B# I/O
B 1 1 1 Common
E 2 2 2
Separate - 2 CH
K 4 2 2 Separate - 2 CH
M 4 4 4 Separate - 2 CH
Q 8 4 4 Separate - 4 CH
Operating Voltage Range
C = V
CC
: 3.3V (2.7–3.6V), V
CCQ
: 1.8V (1.7–1.95V)
Design Revision
C = Third revision
Production Status
Blank = Production
ES = Engineering sample
Special Options
R = MLC plus
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Speed Grade (NV-DDR2 mode only)
-6 = 333 MT/s
Package Code
H6 = 152-ball VBGA 14mm x 18mm x 1.0mm
1
H7 = 152-ball TBGA 14mm x 18mm x 1.2mm
1
H8 = 152-ball LBGA 14mm x 18mm x 1.4mm
1
Interface
B = Sync/Async
Generation Feature Set
C = Third set of device features
2T = 2Tb
G2 = 272-ball LFBGA 14mm x 18mm x 1.3mm
1
G6 = 272-ball LFBGA 14mm x 18mm x 1.5mm
1
U 8 4 4 Separate - 2 CH
V 16 8 4
Separate - 4 CH
R
T 16 8 4
Separate - 2 CH
L 4 4 4
Separate - 4 CH
G1 = 272-ball VFBGA 14mm x 18mm x 1.0mm
1
J7 = 152-ball LBGA 14mm x 18mm x 1.5mm
1
Note:
1. Pb-free package.
Micron Confidential and Proprietary
MLC 128Gb to 2Tb Async/Sync NAND
Features
PDF: 09005aef8569746c
L95B_pluc_128_256_512Gb_1Tb_2Tb_Async_Sync_NAND.pdf Rev. F 1/19/18 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Contents
Important Notes and Warnings ....................................................................................................................... 12
General Description ....................................................................................................................................... 13
Asynchronous, NV-DDR, and NV-DDR2 Signal Descriptions ............................................................................ 13
Signal Assignments ......................................................................................................................................... 15
Package Dimensions ....................................................................................................................................... 17
Architecture ................................................................................................................................................... 24
Device and Array Organization ........................................................................................................................ 25
Bus Operation – Asynchronous Interface ......................................................................................................... 34
Asynchronous Enable/Standby ................................................................................................................... 34
Asynchronous Bus Idle ............................................................................................................................... 34
Asynchronous Pausing Data Input/Output .................................................................................................. 35
Asynchronous Commands .......................................................................................................................... 35
Asynchronous Addresses ............................................................................................................................ 36
Asynchronous Data Input ........................................................................................................................... 37
Asynchronous Data Output ......................................................................................................................... 38
Write Protect .............................................................................................................................................. 39
Ready/Busy# .............................................................................................................................................. 39
Bus Operation – NV-DDR Interface ................................................................................................................. 43
NV-DDR Enable/Standby ............................................................................................................................ 44
NV-DDR Bus Idle/Driving ........................................................................................................................... 44
NV-DDR Pausing Data Input/Output .......................................................................................................... 45
NV-DDR Commands .................................................................................................................................. 45
NV-DDR Addresses ..................................................................................................................................... 46
NV-DDR DDR Data Input ........................................................................................................................... 47
NV-DDR Data Output ................................................................................................................................. 48
Write Protect .............................................................................................................................................. 50
Ready/Busy# .............................................................................................................................................. 50
Bus Operation – NV-DDR2 Interface ................................................................................................................ 51
Differential Signaling .................................................................................................................................. 52
Warmup Cycles .......................................................................................................................................... 52
On-die Termination (ODT) ......................................................................................................................... 53
Self-termination On-die Termination (ODT) ................................................................................................ 54
Matrix Termination .................................................................................................................................... 55
Matrix Termination Examples ..................................................................................................................... 57
NV-DDR2 Standby ...................................................................................................................................... 62
NV-DDR2 Idle ............................................................................................................................................ 63
NV-DDR2 Pausing Data Input/Output ......................................................................................................... 63
NV-DDR2 Commands ................................................................................................................................. 63
NV-DDR2 Addresses ................................................................................................................................... 64
NV-DDR2 Data Input .................................................................................................................................. 65
NV-DDR2 Data Output ............................................................................................................................... 66
Write Protect .............................................................................................................................................. 67
Ready/Busy# .............................................................................................................................................. 67
Device Initialization ....................................................................................................................................... 68
V
PP
Initialization ......................................................................................................................................... 70
Activating Interfaces ....................................................................................................................................... 71
Activating the Asynchronous Interface ........................................................................................................ 71
Activating the NV-DDR Interface ................................................................................................................. 71
Activating the NV-DDR2 Interface ............................................................................................................... 71
CE# Pin Reduction and Volume Addressing ..................................................................................................... 73
Micron Confidential and Proprietary
MLC 128Gb to 2Tb Async/Sync NAND
Features
PDF: 09005aef8569746c
L95B_pluc_128_256_512Gb_1Tb_2Tb_Async_Sync_NAND.pdf Rev. F 1/19/18 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Initialization Sequence ............................................................................................................................... 75
Volume Appointment Without CE# Pin Reduction ....................................................................................... 76
Appointing Volume Addresses ..................................................................................................................... 77
Selecting a Volume ..................................................................................................................................... 77
Multiple Volume Operation Restrictions ...................................................................................................... 77
Volume Reversion ....................................................................................................................................... 78
Command Definitions .................................................................................................................................... 80
Reset Operations ............................................................................................................................................ 83
RESET (FFh) ............................................................................................................................................... 83
SYNCHRONOUS RESET (FCh) .................................................................................................................... 84
RESET LUN (FAh) ....................................................................................................................................... 85
Identification Operations ................................................................................................................................ 86
READ ID (90h) ............................................................................................................................................ 86
READ ID Parameter Tables .......................................................................................................................... 87
READ PARAMETER PAGE (ECh) .................................................................................................................. 88
Parameter Page Data Structure Tables ..................................................................................................... 90
READ UNIQUE ID (EDh) ........................................................................................................................... 106
Configuration Operations .............................................................................................................................. 108
SET FEATURES (EFh) ................................................................................................................................. 108
GET FEATURES (EEh) ................................................................................................................................ 109
GET/SET FEATURES by LUN (D4h/D5h) .................................................................................................... 109
VOLUME SELECT (E1h) ............................................................................................................................. 118
ODT CONFIGURE (E2h) ............................................................................................................................ 120
Status Operations .......................................................................................................................................... 123
READ STATUS (70h) .................................................................................................................................. 124
READ STATUS ENHANCED (78h) ............................................................................................................... 125
Column Address Operations .......................................................................................................................... 125
CHANGE READ COLUMN (05h-E0h) ......................................................................................................... 126
CHANGE READ COLUMN ENHANCED (06h-E0h) ...................................................................................... 126
CHANGE READ COLUMN ENHANCED (00h-05h-E0h) Operation ............................................................... 127
CHANGE WRITE COLUMN (85h) ............................................................................................................... 127
CHANGE ROW ADDRESS (85h) .................................................................................................................. 128
Read Operations ............................................................................................................................................ 130
READ MODE (00h) .................................................................................................................................... 132
READ PAGE (00h-30h) ............................................................................................................................... 133
READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 134
READ PAGE CACHE RANDOM (00h-31h) ................................................................................................... 135
READ PAGE CACHE LAST (3Fh) ................................................................................................................. 137
READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 138
Read Retry Operations ............................................................................................................................... 140
Program Operations ...................................................................................................................................... 142
PROGRAM PAGE (80h-10h) ........................................................................................................................ 142
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 144
PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................ 146
Erase Operations ........................................................................................................................................... 148
ERASE BLOCK (60h-D0h) ........................................................................................................................... 148
ERASE BLOCK MULTI-PLANE (60h-D1h) ................................................................................................... 149
ERASE BLOCK MULTI-PLANE (60h-60h-D0h) ............................................................................................ 149
Copyback Operations .................................................................................................................................... 150
COPYBACK READ (00h-35h) ...................................................................................................................... 151
COPYBACK PROGRAM (85h–10h) .............................................................................................................. 152
COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 152
Micron Confidential and Proprietary
MLC 128Gb to 2Tb Async/Sync NAND
Features
PDF: 09005aef8569746c
L95B_pluc_128_256_512Gb_1Tb_2Tb_Async_Sync_NAND.pdf Rev. F 1/19/18 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 153
One-Time Programmable (OTP) Operations ................................................................................................... 153
PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 154
PROTECT OTP AREA (80h-10h) .................................................................................................................. 156
READ OTP PAGE (00h-30h) ........................................................................................................................ 157
Multi-Plane Operations ................................................................................................................................. 158
Multi-Plane Addressing ............................................................................................................................. 158
Interleaved Die (Multi-LUN) Operations ......................................................................................................... 158
Error Management ........................................................................................................................................ 160
Shared Pages ................................................................................................................................................. 161
Output Drive Impedance ............................................................................................................................... 165
AC Overshoot/Undershoot Specifications ....................................................................................................... 167
Input Slew Rate ............................................................................................................................................. 169
Output Slew Rate ........................................................................................................................................... 176
Power Cycle Requirements ............................................................................................................................. 178
Electrical Specifications ................................................................................................................................. 179
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 182
Electrical Specifications – DC Characteristics and Operating Conditions (NV-DDR and NV-DDR2) ................... 182
Electrical Specifications – DC Characteristics and Operating Conditions (V
CCQ
) ............................................... 183
Single-Ended Requirements for Differential signals ..................................................................................... 185
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 186
Electrical Specifications – AC Characteristics and Operating Conditions (NV-DDR and NV-DDR2) .................... 189
Electrical Specifications – Array Characteristics .............................................................................................. 202
Asynchronous Interface Timing Diagrams ...................................................................................................... 203
NV-DDR Interface Timing Diagrams .............................................................................................................. 213
NV-DDR2 Interface Timing Diagrams ............................................................................................................. 235
Revision History ............................................................................................................................................ 258
Rev. F Production – 1/19/18 ....................................................................................................................... 258
Rev. E Production – 9/30/16 ....................................................................................................................... 258
Rev. D – 8/14 ............................................................................................................................................. 258
Rev. C – 3/14 .............................................................................................................................................. 259
Rev. B – 1/28/14 ......................................................................................................................................... 259
Rev. A – 10/11/13 ....................................................................................................................................... 260
Micron Confidential and Proprietary
MLC 128Gb to 2Tb Async/Sync NAND
Features
PDF: 09005aef8569746c
L95B_pluc_128_256_512Gb_1Tb_2Tb_Async_Sync_NAND.pdf Rev. F 1/19/18 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
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