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TMS320F28069完整手册

该档案是TI公司的28069芯片的技术参考手册,其中包括系统控制和中断、增强型脉冲宽度调制器(ePWM)模块、高分辨率脉冲宽度调制器(HRPWM)、增强型捕获(eCAP)模块、模数转换器和比较器等全部模块。
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Preliminary
TMS320x2806x Piccolo
Technical Reference Manual
Literature Number: SPRUH18C
April 2011– Revised December 2011

Contents
Preface ...................................................................................................................................... 45
1 Systems Control and Interrupts ........................................................................................... 47
1.1 Flash and OTP Memory Blocks ......................................................................................... 48
1.1.1 Flash Memory ..................................................................................................... 48
1.1.2 OTP Memory ...................................................................................................... 48
1.1.3 Flash and OTP Power Modes .................................................................................. 49
1.1.4 Flash and OTP Registers ....................................................................................... 54
1.2 Code Security Module (CSM) ............................................................................................ 60
1.2.1 Functional Description ........................................................................................... 60
1.2.2 CSM Impact on Other On-Chip Resources ................................................................... 62
1.2.3 Incorporating Code Security in User Applications ............................................................ 62
1.2.4 Do's and Don'ts to Protect Security Logic ..................................................................... 68
1.2.5 CSM Features - Summary ...................................................................................... 68
1.3 Clocking ..................................................................................................................... 69
1.3.1 Clocking and System Control ................................................................................... 69
1.3.2 OSC and PLL Block .............................................................................................. 76
1.3.3 Low-Power Modes Block ........................................................................................ 97
1.3.4 CPU Watchdog Block ............................................................................................ 99
1.3.5 32-Bit CPU Timers 0/1/2 ....................................................................................... 105
1.4 General-Purpose Input/Output (GPIO) ................................................................................ 110
1.4.1 GPIO Module Overview ........................................................................................ 110
1.4.2 Configuration Overview ........................................................................................ 116
1.4.3 Digital General Purpose I/O Control .......................................................................... 118
1.4.4 Input Qualification ............................................................................................... 119
1.4.5 GPIO and Peripheral Multiplexing (MUX) .................................................................... 124
1.4.6 Register Bit Definitions ......................................................................................... 129
1.5 Peripheral Frames ....................................................................................................... 150
1.5.1 Peripheral Frame Registers ................................................................................... 150
1.5.2 EALLOW-Protected Registers ................................................................................. 152
1.5.3 Device Emulation Registers ................................................................................... 156
1.5.4 Write-Followed-by-Read Protection .......................................................................... 159
1.6 Peripheral Interrupt Expansion (PIE) .................................................................................. 160
1.6.1 Overview of the PIE Controller ................................................................................ 160
1.6.2 Vector Table Mapping .......................................................................................... 163
1.6.3 Interrupt Sources ................................................................................................ 165
1.6.4 PIE Configuration Registers ................................................................................... 174
1.6.5 PIE Interrupt Registers ......................................................................................... 175
1.6.6 External Interrupt Control Registers .......................................................................... 183
1.7 VREG/BOR/POR ......................................................................................................... 185
1.7.1 On-chip Voltage Regulator (VREG) .......................................................................... 185
1.7.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit .................................. 186
2 Boot ROM ....................................................................................................................... 187
2.1 Boot ROM Memory Map ................................................................................................ 188
2.1.1 On-Chip Boot ROM Math Tables ............................................................................. 189
2.1.2 On-Chip Boot ROM IQmath Functions ....................................................................... 191
3
SPRUH18C – April 2011–Revised December 2011 Contents
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Copyright © 2011, Texas Instruments Incorporated

Preliminary
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2.1.3 On-Chip Flash API .............................................................................................. 191
2.1.4 CPU Vector Table ............................................................................................... 191
2.2 Bootloader Features ..................................................................................................... 194
2.2.1 Bootloader Functional Operation .............................................................................. 194
2.2.2 Bootloader Device Configuration .............................................................................. 195
2.2.3 PLL Multiplier and DIVSEL Selection ........................................................................ 196
2.2.4 Watchdog Module ............................................................................................... 196
2.2.5 Taking an ITRAP Interrupt ..................................................................................... 196
2.2.6 Internal Pullup Resisters ....................................................................................... 197
2.2.7 PIE Configuration ............................................................................................... 197
2.2.8 Reserved Memory .............................................................................................. 197
2.2.9 Bootloader Modes ............................................................................................... 198
2.2.10 Device_Cal ...................................................................................................... 204
2.2.11 Bootloader Data Stream Structure .......................................................................... 204
2.2.12 Basic Transfer Procedure ..................................................................................... 209
2.2.13 InitBoot Assembly Routine .................................................................................... 210
2.2.14 SelectBootMode Function .................................................................................... 211
2.2.15 CopyData Function ............................................................................................ 214
2.2.16 SCI_Boot Function ............................................................................................. 214
2.2.17 Parallel_Boot Function (GPIO) ............................................................................... 216
2.2.18 SPI_Boot Function ............................................................................................. 221
2.2.19 I2C Boot Function .............................................................................................. 224
2.2.20 eCAN Boot Function ........................................................................................... 227
2.2.21 ExitBoot Assembly Routine .................................................................................. 229
2.3 Building the Boot Table ................................................................................................. 230
2.3.1 The C2000 Hex Utility .......................................................................................... 230
2.3.2 Example: Preparing a COFF File For eCAN Bootloading ................................................. 231
2.4 Bootloader Code Overview ............................................................................................. 235
2.4.1 Boot ROM Version and Checksum Information ............................................................. 235
3 Enhanced Pulse Width Modulator (ePWM) Module ............................................................... 237
3.1 Introduction ............................................................................................................... 238
3.1.1 Submodule Overview ........................................................................................... 238
3.1.2 Register Mapping ............................................................................................... 241
3.2 ePWM Submodules ...................................................................................................... 244
3.2.1 Overview ......................................................................................................... 244
3.2.2 Time-Base (TB) Submodule ................................................................................... 246
3.2.3 Counter-Compare (CC) Submodule .......................................................................... 257
3.2.4 Action-Qualifier (AQ) Submodule ............................................................................. 263
3.2.5 Dead-Band Generator (DB) Submodule ..................................................................... 278
3.2.6 PWM-Chopper (PC) Submodule .............................................................................. 283
3.2.7 Trip-Zone (TZ) Submodule .................................................................................... 287
3.2.8 Event-Trigger (ET) Submodule ................................................................................ 292
3.2.9 Digital Compare (DC) Submodule ............................................................................ 296
3.3 Applications to Power Topologies ..................................................................................... 303
3.3.1 Overview of Multiple Modules ................................................................................. 303
3.3.2 Key Configuration Capabilities ................................................................................ 303
3.3.3 Controlling Multiple Buck Converters With Independent Frequencies ................................... 304
3.3.4 Controlling Multiple Buck Converters With Same Frequencies ........................................... 308
3.3.5 Controlling Multiple Half H-Bridge (HHB) Converters ...................................................... 311
3.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ......................................... 313
3.3.7 Practical Applications Using Phase Control Between PWM Modules ................................... 317
3.3.8 Controlling a 3-Phase Interleaved DC/DC Converter ...................................................... 318
3.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter ...................................... 322
4
Contents SPRUH18C – April 2011–Revised December 2011
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Copyright © 2011, Texas Instruments Incorporated

Preliminary
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3.3.10 Controlling a Peak Current Mode Controlled Buck Module .............................................. 324
3.3.11 Controlling H-Bridge LLC Resonant Converter ............................................................ 326
3.4 Registers .................................................................................................................. 329
3.4.1 Time-Base Submodule Registers ............................................................................. 329
3.4.2 Counter-Compare Submodule Registers .................................................................... 336
3.4.3 Action-Qualifier Submodule Registers ....................................................................... 340
3.4.4 Dead-Band Submodule Registers ............................................................................ 343
3.4.5 PWM-Chopper Submodule Control Register ................................................................ 346
3.4.6 Trip-Zone Submodule Control and Status Registers ....................................................... 348
3.4.7 Digital Compare Submodule Registers ...................................................................... 355
3.4.8 Event-Trigger Submodule Registers ......................................................................... 360
3.4.9 Proper Interrupt Initialization Procedure ..................................................................... 366
4 High-Resolution Pulse Width Modulator (HRPWM) ............................................................... 367
4.1 Introduction ............................................................................................................... 368
4.2 Operational Description of HRPWM ................................................................................... 370
4.2.1 Controlling the HRPWM Capabilities ......................................................................... 371
4.2.2 Configuring the HRPWM ....................................................................................... 373
4.2.3 Principle of Operation .......................................................................................... 374
4.2.4 Scale Factor Optimizing Software (SFO) .................................................................... 383
4.2.5 HRPWM Examples Using Optimized Assembly Code. .................................................... 384
4.3 HRPWM Register Descriptions ........................................................................................ 390
4.3.1 Register Summary .............................................................................................. 390
4.3.2 Registers and Field Descriptions ............................................................................. 391
4.4 Appendix A: SFO Library Software - SFO_TI_Build_V6.lib ........................................................ 395
4.4.1 Scale Factor Optimizer Function - int SFO() ................................................................ 395
4.4.2 Software Usage ................................................................................................. 396
4.4.3 SFO Library Version Software Differences .................................................................. 397
5 High Resolution Capture ................................................................................................... 399
5.1 Introduction ............................................................................................................... 400
5.2 Description ................................................................................................................ 400
5.3 Operational Details ...................................................................................................... 401
5.3.1 HRCAP Clocking ................................................................................................ 401
5.3.2 HRCAP Modes of Operation .................................................................................. 402
5.3.3 HRCAP Interrupts ............................................................................................... 405
5.4 Register Descriptions .................................................................................................... 406
5.4.1 HRCAP Control Register (HCCTL) – EALLOW protected ................................................. 406
5.4.2 HRCAP Interrupt Flag Register (HCIFR) .................................................................... 407
5.4.3 HRCAP Interrupt Clear Register (HCICLR) ................................................................. 408
5.4.4 HRCAP Interrupt Force Register (HCIFRC) ................................................................. 409
5.4.5 HRCAP Counter Register (HCCOUNTER) .................................................................. 409
5.4.6 HRCAP Capture Counter On Rising Edge 0 Register (HCCAPCNTRISE0) ............................ 410
5.4.7 HRCAP Capture Counter On Rising Edge 1 Register (HCCAPCNTRISE1) ............................ 410
5.4.8 HRCAP Capture Counter On Falling Edge 0 Register (HCCAPCNTFALL0) ........................... 410
5.4.9 HRCAP Capture Counter On Falling Edge 1 Register (HCCAPCNTFALL1) ........................... 411
5.5 HRCAP Calibration Library ............................................................................................. 411
5.5.1 HRCAP Calibration Library Functions ........................................................................ 412
5.5.2 HRCAP Calibration Library Software Usage ................................................................ 416
6 Enhanced Capture (eCAP) Module ..................................................................................... 419
6.1 Introduction ............................................................................................................... 420
6.2 Description ................................................................................................................ 420
6.3 Capture and APWM Operating Mode ................................................................................. 421
6.4 Capture Mode Description .............................................................................................. 421
6.4.1 Event Prescaler ................................................................................................. 422
5
SPRUH18C – April 2011– Revised December 2011 Contents
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Copyright © 2011, Texas Instruments Incorporated
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