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11/23/2005 11797
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5650X-PG102-R
16215 Alton Parkway • P.O. Box 57013 • Irvine, CA 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710 10/20/05
Programmer’s Guide
BCM5650X
Theory of Operations
11/23/2005 11797
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BCM5650X Programmer’s Guide
10/20/05
Broadcom Corporation
Page ii Document 5650X-PG102-R
REVISION HISTORY
Revision Date Description
5650X-PG102-R 10/20/05 Updated:
• L2 Unicast MAC Addresses’ feature 13,384 to 16,384 in Table 2: “BCM5630X/
BCM5610X Family Versus BCM5650X Family Features,” on page 2
• Second paragraph in “Virtual Local Area Network” on page 27.
• Figure 14: “Unqualified Configuration,” on page 30.
• In “Transparent Service Mode” on page 31:
- Uplink to NNI (uplink).
- Access to UNI (access).
•
The SPVLAN tag is based on protocol or port-based VLAN tables
to
The SPVLAN tag is
based on the VLAN translation protocol, subnet-based protocol, MAC-based protocol, or
port-based VLAN tables
in “Ingress on a UNI (Access) Port” on page 31.
•
A packet is considered as DT if the inner TPID matches the
IGR_VLAN_CONTROL.INNER_TPID (single tag)...
to
A packet is considered as DT if the
inner TPID matches the IGR_VLAN_CONTROL.INNER_TPID...
in “Ingress on an NNI
(Uplink) Port” on page 32.
• In “Mapped Service Mode” on page 34
:
- Uplink to NNI (uplink).
- Access to UNI (access).
- PORT.VT_ENBABLE to PORT.VT_ENBABLE.
• “VLAN Translation” on page 34.
• In “L3 Feature List and Operations” on page 38:
- Layer 3 (IPv4 routing) to IPv4 and IPv6 routing
- Layer 3 (IPv6 routing) to IPv4 and IPv6 multicast
• 6384 to 6144 entries in the L3_DEFIP table in “L3_DEFIP IPv4 Longest Prefix Match
Table” on page 39.
• Third paragraph in “IP Multicast” on page 41.
• “IPMC Replication” on page 42.
• Descriptions for IBPCELLSETLIMIT and IBPCELLSETLIMIT registers in
Table 10: “Threshold Limits,” on page 47.
• The Hercules to a HiGig in “End-to-End Ingress Back Pressure” on page 58.
•
The mechanism uses the same special 64-byte packet as in the E2E IBP mechanism
to
The mechanism uses a similar 64-byte packet as in the E2E IBP mechanism
in “End-to-
End HOL” on page 61.
• “Link Aggregation GbE/10-GbE (Trunking)” on page 77.
• “sFlow Traffic Monitoring” on page 93.
• IMPC_INDEX to IPMC_INDEX in step 3 a. in “IPv6/IPMCv6 Support for Legacy
Devices” on page 100.
Added:
• To “Transparent and Mapped Services” on page 29:
- First and second paragraphs.
- Figure 15: “Provider Bridging Architecture,” on page 30.
• IP-IP (encapsulation of IPv4 in IPv4) to “IP Tunneling” on page 40.
• Note to “Traffic Metering/Shaping” on page 62.
• “Packet Size Adjustment” on page 68.
• IPv6/tunneling proxy support for XGSII devices using BCM56603 in “Enhanced Feature
List and Operations” on page 72.
• Figure 38: “Unicast LAG Resolution,” on page 78.
• “Trunk Resolution for Non-Unicast” on page 81.
11/23/2005 11797
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Programmer’s Guide BCM5650X
10/20/05
Broadcom Corporation
Document 5650X-PG102-R Page iii
5650X-PG102-R
(Cont.)
10/20/05 Removed:
• From “L2 Feature List and Operations” on page 24:
- L2 table size bullet
- IP multicast bullet from “L3 Feature List and Operations” on page 38.
•
An uplink port is connected to the service provider. An access port is connected to the
customer
from “Transparent and Mapped Services” on page 29.“Bits on the Wire.”
• “Time on the Wire.”
•
Although implementing this rate control feature on a more granular level improves
performance
from “End-to-End Ingress Back Pressure” on page 58.
•
That the minimum and maximum metering mechanisms can be used in conjunction with
the DRR mode, which allows specifying a possibly equal distribution of bandwidth for the
minimum bandwidth requirements and then a weighted distribution of bandwidth
allocation when servicing bandwidth larger than the minimum allocation. Also that
maximum bandwidth shaping could also be used to limit bandwidth allocated to a specific
CoS queue
. from “Deficit Round Robin” on page 69.
• Non-unicast packet information from “In this mode, the index value is the XOR of mode
4 and mode 5 results.” on page 80.
• IEEE 802.1aa compatible bullet from “Port Security” on page 88.
5650X-PG101-R 06/14/05 Updated:
• In “Introduction”:
- Table 1: BCM5610X, BCM5630X, BCM5650X, and BCM5660X Device Differences.
- Table 2: BCM5630X Family vs. BCM5650X Family Features.
• In “Architectural Overview”:
- “BroadScale Architecture.”
- “Pipeline Blocks: Intelligent Parser, L2 Switching, ContentAware Processing.”
- “Memory Management Unit: Packet Buffer Structure and Accounting, Alternate Store
and Forward.”
• L2 Ingress Packet on GbE/10-GbE Ports in “Packet Flow.”
• In “L2 Feature List and Operations”:
- “Virtual Local Area Network.“
- “Transparent and Mapped Services.“
- “Ingress on an Access Port.“
• In “L3 Feature List and Operations”:
- “Layer 3 (IPv4 Routing).“
- “L3_DEFIP IPv4 Longest Prefix Match“ table.
- “Layer 3 (IPv6 Routing).“
- “L3_DEFIP IPv6 Longest Prefix Match“ table.
- “IP Tunneling.“
- “IPMC Replication.“
• In “Buffer Management Mechanisms”:
- “PAUSE Metering.“
- “Congestion Bits.“
- “Scheduler Modes. Deficit Round Robin.“
• In “Enhanced Feature List and Operations”:
- “Stacking and Related Information. HiGig+ Module Header Information” table.
- “Mirroring.”
- “Mirroring: Ingress Mirroring.”
- “Mirroring: Egress Mirroring.”
- “Mirroring: RSPAN Mirroring.”
Revision Date Description
11/23/2005 11797
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Broadcom
®
, the pulse logo, Connecting everything
®
, the Connecting everything logo, StrataXGS
®
, BroadScale™,
ContentAware™, BroadSAFE™, StrataXGS II™, and StrataXGS III™ are among the trademarks of Broadcom
Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade
names mentioned are the property of their respective owners.
Broadcom Corporation
P.O. Box 57013
16215 Alton Parkway
Irvine, CA 92619-7013
© 2005 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
5650X-PG101-R
(Cont.)
06/14/05 Updated:
• In “Introduction”:
- Table 1: BCM5610X, BCM5630X, BCM5650X, and BCM5660X Device Differences.
- Table 2: BCM5630X Family vs. BCM5650X Family Features.
• In “Architectural Overview”:
- “BroadScale Architecture.”
- “Pipeline Blocks: Intelligent Parser, L2 Switching, ContentAware Processing.”
- “Memory Management Unit: Packet Buffer Structure and Accounting, Alternate Store
and Forward.”
• L2 Ingress Packet on GbE/10-GbE Ports in “Packet Flow.”
• In “L2 Feature List and Operations”:
- “Virtual Local Area Network.“
- “Transparent and Mapped Services.“
- “Ingress on an Access Port.“
• In “L3 Feature List and Operations”:
- “Layer 3 (IPv4 Routing).“
- “L3_DEFIP IPv4 Longest Prefix Match“ table.
- “Layer 3 (IPv6 Routing).“
- “L3_DEFIP IPv6 Longest Prefix Match“ table.
- “IP Tunneling.“
- “IPMC Replication.“
• In “Buffer Management Mechanisms”:
- “PAUSE Metering.“
- “Congestion Bits.“
- “Scheduler Modes. Deficit Round Robin.“
• In “Enhanced Feature List and Operations”:
- “Stacking and Related Information. HiGig+ Module Header Information” table.
- “Mirroring.”
- “Mirroring: Ingress Mirroring.”
- “Mirroring: Egress Mirroring.”
- “Mirroring: RSPAN Mirroring.”
Added:
• “Fast Ethernet Port Interface Block.”
• “VLAN Translation.”
• “HiGig Lookup in BCM5650X B0 Devices.”
• “Mirroring: MAC-Based Mirroring.”
• “Mirroring: HiGig Mirroring.”
• “Appendix A.”
5650X-PG100-R 11/30/04 Initial release.
Revision Date Description
11/23/2005 11797
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Programmer’s Guide BCM5650X
10/20/05
Broadcom Corporation
Document 5650X-PG102-R Page v
TABLE OF CONTENTS
Section 1: Introduction........................................................................................................1
Audience ....................................................................................................................................................... 1
Device Nomenclature................................................................................................................................... 1
BCM5630X/BCM5610X Product Family Overview ..................................................................................... 2
BCM5610X Family Overview ....................................................................................................................... 2
Section 2: Architectural Overview......................................................................................3
BroadScale™ Architecture.......................................................................................................................... 4
Pipeline Blocks............................................................................................................................................. 5
Intelligent Parser ..................................................................................................................................... 5
Security Engine....................................................................................................................................... 5
L2 Switching............................................................................................................................................ 5
L3 Routing............................................................................................................................................... 5
ContentAware™ Processing................................................................................................................... 6
Buffer Management ................................................................................................................................ 6
Traffic Management ................................................................................................................................ 6
Modification............................................................................................................................................. 6
Fast Ethernet Port Interface Controller Block ........................................................................................... 7
Gigabit Ethernet Port Interface Controller Block ...................................................................................... 7
XPIC/IPIC Interconnect Port Interface Controller...................................................................................... 7
Memory Management Unit .......................................................................................................................... 8
Buffer Management Overview ................................................................................................................ 8
Packet Buffer Structure and Accounting ................................................................................................. 9
Alternate Store and Forward ................................................................................................................. 10
Look-Up Tables .......................................................................................................................................... 11
Search Engines .......................................................................................................................................... 13
Binary Search Engine ........................................................................................................................... 14
Hash Search Engine ............................................................................................................................. 14
CAM Search Engine ............................................................................................................................. 14
ContentAware™ Processor....................................................................................................................... 15
Intelligent Protocol-Aware Selector....................................................................................................... 15
ContentAware Lookup Engine .............................................................................................................. 15
ContentAware Policy Engine ................................................................................................................ 15
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