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MT6755
LTE-A Smartphone Application Processor
Technical Brief
Confidential A
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Figure 2-16. MSDC clock timing diagram of DDR50 speed mode. ......................................................... 52
Figure 2-17. MSDC input/output timing diagram of DDR50 speed mode ............................................. 53
Figure 2-18. MSDC clock timing diagram of HS200 ................................................................................ 54
Figure 2-19. MSDC input timing diagram of HS200................................................................................ 54
Figure 2-20. MSDC output timing diagram of HS200 ............................................................................. 54
Figure 2-21. MSDC input timing diagram of HS400 ................................................................................. 55
Figure 2-22. MSDC output timing diagram of HS400 ............................................................................. 56
Figure 2-23. Power on sequence ................................................................................................................ 59
Figure 2-24. Block diagram of BBRX-ADC ................................................................................................ 61
Figure 2-25. Block diagram of BBTX ......................................................................................................... 63
Figure 2-26. Block diagram of ETDAC ...................................................................................................... 64
Figure 2-27. Block diagram of DETADC ................................................................................................... 65
Figure 2-28. Block diagram of APC-DAC .................................................................................................. 66
Figure 2-29. Outlines and dimensions of TFBGA 13mm*13.4mm, 873-ball, 0.4mm pitch package .... 69
Figure 2-30. Top marking of MT6755 ........................................................................................................ 72
Table 2-1. Pin coordinate ........................................................................................................................... 20
Table 2-2. Acronym for pin type ................................................................................................................ 26
Table 2-3. Detailed pin description (using LPDDR3) ............................................................................... 27
Table 2-4. Acronym for table of state of pins ............................................................................................ 36
Table 2-5. Absolute maximum ratings for power supply .......................................................................... 37
Table 2-6. Recommended operating conditions for power supply .......................................................... 38
Table 2-7. RTC DC electrical characteristics (DVDD18_IOLT =1.8V) .................................................... 39
Table 2-8. SPI, I2S DC electrical characteristics (DVDD18_IORB =1.8V) ............................................. 40
Table 2-9. I2C0, I2C1, I2C2 DC electrical characteristics (DVDD18_IORB =1.8V) ............................... 40
Table 2-10. I2C3 DC electrical characteristics (DVDD18_IOLB =1.8V) ................................................. 40
Table 2-11. MSDC0 DC electrical characteristics (DVDD28_MSDC0=1.8V) ......................................... 40
Table 2-12. MSDC1 DC electrical characteristics (DVDD28_MSDC1=2.8V/3.3V) ................................ 40
Table 2-13. MSDC1 DC electrical characteristics (DVDD28_MSDC1=1.8V) ........................................... 41
Table 2-14. SIM DC electrical characteristics ............................................................................................ 41
Table 2-15. LPDDR3 AC timing parameter table of external memory interface .................................... 44
Table 2-16. SPI AC timing parameters ...................................................................................................... 46
Table 2-17. I2S AC timing parameters ........................................................................................................47
Table 2-18. I2C AC timing parameters .......................................................................................................47
Table 2-19. MSDC AC timing parameters of default speed ...................................................................... 49
Table 2-20. MSDC AC timing parameters of high speed ......................................................................... 50
Table 2-21. MSDC AC timing parameters of SDR12/SDR25/SDR50/SDR104 mode ............................. 51
Table 2-22. MSDC AC timing parameters of DDR50 speed mode .......................................................... 53
Table 2-23. MSDC AC timing parameters of HS200 ................................................................................. 55
Table 2-24. MSDC AC timing parameters of HS400................................................................................ 56
Table 2-25. SIM AC timing parameters ...................................................................................................... 57
Table 2-26. Mode selection ........................................................................................................................ 58
Table 2-27. Constant tied pins ................................................................................................................... 58
Table 2-28. Baseband downlink specifications ......................................................................................... 62
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