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MIPI CSI2 RX 设计手册,该手册是MAX10 M50 EVAL kit Compatible MIPI D-phy V.1 physical layer using FPGA LVDS/LVCMOS IO and passive network 支持接收1920*1080——30fps_2lanes image from OV5640 in Raw8 format with 672Mbps rate each lanes ;it support Low level Protocol
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Reference Design MIPI CSI2 Receiver
Date: December 16, 2015
Revision: 1.0
`
TABLE OF CONTENTS
DOCUMENT INFORMATION ...................................................................................................................................................... 4
LIST OF TERMS AND ABBREVIATIONS .............................................................................................................................................. 4
1 INTRODUCTION .................................................................................................................................................................... 5
1.1 OVERVIEW ........................................................................................................................................................................... 5
1.2 FEATURES............................................................................................................................................................................ 5
1.3 TOP LEVEL ARCHITECTURE ................................................................................................................................................. 5
2 INSTALLING THE EXAMPLE DESIGN ............................................................................................................................. 7
3 SYSTEM REQUIREMENT .................................................................................................................................................... 9
3.1 HARDWARE REQUIREMENTS ............................................................................................................................................... 9
3.2 SOFTWARE REQUIREMENTS ................................................................................................................................................. 9
4 EXTERNAL INTERFACE .................................................................................................................................................... 10
4.1 OVERVIEW ......................................................................................................................................................................... 10
4.1.1 Pin List Table: .......................................................................................................................................................... 11
5 CLOCK AND RESET DISTRIBUTION .............................................................................................................................. 12
5.1 CSI2 RECEIVER CLOCKING ................................................................................................................................................ 12
5.2 RESET ................................................................................................................................................................................ 12
6 FUNCTIONAL BLOCK DESCRIPTION............................................................................................................................ 13
6.1 LVDS_SERDES BLOCK: .................................................................................................................................................. 13
6.1.1 Block Interface Diagram: ......................................................................................................................................... 14
6.2 SYNC DETECT BLOCK: ........................................................................................................................................................ 14
6.2.1 The sync detect interface Diagram: .......................................................................................................................... 15
6.2.2 Sync detect block Interface Timing: ........................................................................................................................ 15
6.3 LANE MERGING BLOCK: ..................................................................................................................................................... 15
6.3.1 The lane merging interface Diagram: ...................................................................................................................... 16
6.3.2 The lane merging Block Interface Timing: ............................................................................................................... 16
6.4 FRAME DATA BLOCK:......................................................................................................................................................... 17
6.4.1 The frame data interface Diagram: .......................................................................................................................... 17
6.4.2 The frame data Block Interface Timing: ................................................................................................................... 17
7 VERIFICATION PLAN DESCRIPTION ............................................................................................................................ 18
7.1 OVERVIEW ......................................................................................................................................................................... 18
7.2 OV5640 CAMERA OUTPUT VERIFICATION: ......................................................................................................................... 18
7.2.1 OV5640 camera I
2
C configuration: ........................................................................................................................ 18
7.2.2 OV5640 MIPI CSI2 2 lanes interface: .................................................................................................................... 19
7.3 CSI2 MODULE DEBUG: ....................................................................................................................................................... 19
7.4 VERIFICATION THE IMAGE DISPLAY ON COMPUTER DISPLAYER .......................................................................................... 20
8 OPENING THE REFERENCE DESIGN ............................................................................................................................. 22
8.1 OPENING THE QUARTUS II TOP-LEVEL PROJECT ............................................................................................................... 22
8.2 OPENING THE QSYS SYSTEM ............................................................................................................................................. 22
8.3 VIEWING THE PARAMETERS ............................................................................................................................................... 22
8.4 MODIFY AND UPDATE THE MIPI CSI2 CODE ..................................................................................................................... 24
`
9 CONCLUSION ....................................................................................................................................................................... 26
10 REVISION HISTORY ....................................................................................................................................................... 27
`
Document Information
List of Terms and Abbreviations
CSI2 - Camera Serial Interface 2
CCI - Camera Control Interface
I2C - Inter-Integrated Circuit
DT - Data Type
ECC - Error Correction Code
HS - High Speed
LP - Low-Power
MIPI - Mobile Industry Processor Interface
HDMI - High Definition Multimedia Interface
USB - Universal Serial Bus
`
1 Introduction
1.1 Overview
The reference design is designed to convert MIPI data from an OV image sensor into an Avalon Streaming Video
interface. It has been demonstrated with an Omnivision OV5640 sensor but is extendable to any other Image Sensor
with MIPI 2 lanes RX interface raw8 data format.
1.2 Features
Our MAX10 M50 EVAL kit Compatible MIPI D-Phy v1.1 physical layer using FPGA LVDS/LVCMOS IO and passive
network
The reference design receives 1920x1080_30fps_2lanes image from OV5640 in raw8 format with 672Mbps data rate
each lanes on max10 EVAL kit
It support Pixel to Byte Packing function
It support Low Level Protocol
Lane Management
It support Data format RAW8
The design support 1 ,2 data lanes
Support CCI(Camera control interface) /I2C
Compatible with D-PHY Configured for 1 clock and 2 data lanes.
Verifies CSI-2 header ECC field
Transmits Avalon Streaming Video
1.3 Top Level Architecture
The Figure 1-1 show the high level block diagram of MIPI CSI2 RX reference design in FPGA. The MIPI CSI2 RX
reference design is designed to convert MIPI data from an OV image sensor into an Avalon Streaming Video interface,
it output the raw8 frame data for Imaging process module, then use the HDMI interface to transfer 1080p data, at last,
it display on the computer displayer. It has been demonstrated the demo with an Omnivision OV5640 sensor but is
extendable to any other Image Sensor with a MIPI 2 lanes RX interface raw8 data format.
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