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This document describes Altera TimeQuest timing constraints and analysis for synchronous and asynchronous interfaces, Including a sample project.
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TimeQuest Constraints Analysis
D. W. Hawkins (dwh@ovro.caltech.edu)
Version 0.1
September 5, 2011
Contents
1 Introduction 3
2 Timing Analysis Examples 4
2.1 Synchronous Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Input setup and hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 Output clock-to-output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Asynchronous SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.1 Interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.2 Controller design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A Instructions 43
A.1 Synthesis and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
A.2 TimeQuest Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2
TimeQuest Constraints September 5, 2011
1 Introduction
This document describes Altera TimeQuest timing constraints and analysis for synchronous and
asynchronous interfaces. The main purpose of the document is to provide example designs to disc uss
with Altera Forum member Rysc (Ryan Scoville); the forum’s resident TimeQuest expert.
First, lets review the resources for understanding how to use TimeQuest;
• Altera’s TimeQuest Timing Analyzer Resource Center.
This page is the best starting point for TimeQuest, as it has links to Altera’s documentation
and online courses. For example;
– The TimeQuest Analyzer Quick Start Tutorial [2]
– The TimeQuest Cookbook [5]
– The SDC and TimeQuest API reference manual [1]
• The Quartus II Handbook [4] discusses TimeQuest in Volume 3, Chapters 6, 7, and 8.
• The Altera Wiki has Ryan’s TimeQuest User’s Guide (the lates t version was dated 9 December
2010)
• The Altera Forum discussion thread 1269 has a document describing asynchronous SRAM
constraints in an SOPC System (the second page of the thread has an updated document
version 1.1).
The Quartus II handbook discusses synchronous and asynchronous paths as they relate to syn-
chronous registers, however, it does not discuss analyzing the timing between the synchronous out-
puts of the FPGA, and an asynchronous external device, such as SRAM. The TimeQuest Quickstart
Tutorial has nothing on asynchronous interfaces. The TimeQuest Cookbook has a brief comment
on tri-state outputs (p1-13), however, it makes no comment on why the output delay constraints
require defining a virtual clock. The Alte ra forum thread 1269 document does discuss SRAM con-
straints, however, it magically states the FPGA timing parameters (setup and hold for inputs, and
clock-to-output minimum and maximum delays for outputs), and then uses those magical numbers
to determine how many FPGA clocks are needed to meet the SRAM timing requirements.
In this document, based on the approach given in Ryan’s document, I show that constraining
an SRAM interface is an iterative procedure. The analysis starts with FPGA timing constraints
set to zero, and those unrealistic parameters are used along with the SRAM timing parameters to
determine how many clocks the FPGA SRAM controller needs to assert the SRAM c ontrol signals.
The design is then placed-and-routed, a timing analysis is performed, and the actual (realistic) FPGA
timing parameters are extracted. Those updated FPGA parameters are then used to re-calculate
the FPGA SRAM controller timing, and the timing analysis is repeated.
There are several things that can affect the FPGA I/O timing, without changing the HDL that
describes a design, eg., the timing model used for analysis (fast and slow timing models), and FPGA
I/O options, such as enabling or disabling fast IOE output or input registers. This document looks
at the variation in timing for each of these options. A rock-solid design should use the worst-case
timing when determining the number of clock cycles to drive external asynchronous control signals.
The document provides an example design for the SRAM on the Arrow BeMicro USB board.
I’ll add examples for the DE2, DE2-70, and DE2-115 SRAMs after I’ve had some feedback on this
first revision. The timing analysis of the BeMicro shows that not all I/O pins are created equal; the
VREF pins have much larger output delays.
3
TimeQuest Constraints September 5, 2011
clk
d[7:0]
q[7:0]
t
S
t
CO(min)
t
H
t
CO(max)
D Q
CLK
D Q
CLK
D Q
CLK
FPGAExternal Source External Destination
d[7:0] q[7:0]
clk
(a)
(b)
Figure 1: Register timing parameters; (a) input and output registers path, and (b) FPGA registers
timing parameters.
2 Timing Analysis Examples
Figure 1 shows the timing parameters of a synchronous timing path involving an 8-bit FPGA register.
The timing uncertainty on the FPGA input signal d[7:0], is due to the external source register
clock-to-output delay uncertainty. The FPGA input signal must satisfy the FPGA input register
setup and hold times (shown in the figure in blue). The FPGA outputs the signal q[7:0] after the
FPGA clock-to-output delay (shown in the figure in red). The timing of the output signal q[7:0],
must satisfy the destination register setup and hold times.
TimeQuest I/O timing constraints are generally based on the timing parameters of the external
devices; where that timing information is provided in the external device data sheets. Setting up
these constraints for FPGA-to-FPGA data paths, or FPGA-to-asynchronous memory data paths,
becomes a little trickier, as the parameters are either not specified (eg., the FPGA timing parame-
ters), or the relationship between the asynchronous external device timing parameters and those of
an equivalent synchronous design, are not obvious.
The examples in this section help clarify the external device timing parameters, the FPGA timing
parameters, and the TimeQuest constraints.
4
TimeQuest Constraints September 5, 2011
Table 1: External device timing parameters.
Timing Parameter Minimum Maximum
External Source
Clock-to-output delay 0.5 3.0
External Destination
Setup time 1.5
Hold time 1.0
2.1 Synchronous Interfaces
Figure 2 shows a simple synchronous design c ontaining a registers component with a parameterized
width. The component deliberately avoids using an asynchronous reset port, to avoid TimeQuest
analyzing that path.
Synthesis of the design in Figure 2 requires additional constraints;
• Synthesis constraints
– Device assignment
– Pin assignment
– Functionality assignments, eg. use fast I/O registers
• Timing analysis constraints
– A TimeQuest SDC file
The projec t source contains two Tcl scripts that implement these constraints. The source layout of
the project is;
• vhdl/registers/src/registers.vhd
The VHDL source.
• vhdl/registers/scripts/registers.sdc
TimeQuest timing constraints; for a 100MHz FPGA clock (10ns period), and the external
device timing shown in Table 1. Each of the external device timing parameters is unique, so
that it can be identified in the TimeQuest timing reports.
• vhdl/registers/scripts/tmq_report.tcl
A Tcl script for post-synthesis timing analysis reporting.
• vhdl/registers/scripts/synth.tcl
Quartus II synthesis script; this script creates a Quartus project, adds the VHDL and SDC
files, assigns pin constraints, and synthesizes the design.
The design can be synthesized using the Quartus II Tcl console (View→Utility Windows→Tcl
Console), by changing to the registers directory, and then running the synthesis script via the Tcl
command source scripts/synth.tcl.
5
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