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Document Number: IBL# 541356
Intel
®
Extreme Memory Profile
(Intel
®
XMP) 2.0
Specification
Enthusiast Extension to the JEDEC DDR4 SPD Specification
December 2013
Revision 1.0
Intel Confidential
2 Intel Confidential IBL# 541356
NFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death.
SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND
ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL
CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT
LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS
SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or
characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice.
Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-
4725, or go to: http://www.intel.com/design/literature.htm.
Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release.
Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or
services and any such use of Intel's internal code names is at the sole risk of the user.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, Ultrabook, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2013, Intel Corporation. All Rights Reserved.
IBL# 541356 Intel Confidential 3
Contents
1Introduction..............................................................................................................7
2 Address Map..............................................................................................................8
2.1 Address Map.......................................................................................................8
2.2 Global Bytes 384 to 392..................................................................................... 10
2.2.1 Byte 384 and 385: Intel
®
XMP Identification String.....................................10
2.2.2 Byte 386: Intel® XMP Organization & Configuration....................................11
2.2.3 Byte 387: Intel
®
XMP Revision.................................................................11
2.2.4 Byte 388: Timebases for Profile 1.............................................................12
2.2.5 Byte 389: Timebases for Profile 2.............................................................12
2.2.6 Bytes 390,391,392: RFU .........................................................................14
2.3 Details of Each Byte 393 to 486 .......................................................................... 14
2.3.1 Byte 393 or 440: Module VDD Voltage Level ..............................................15
2.3.2 Bytes 394/395 or 441/442: RFU...............................................................15
2.3.3 Byte 396 or 443: Minimum SDRAM Cycle Time (t
CKAVGmin
) ..........................16
2.3.4 Byte 397 or 444: CAS Latencies Supported, First Byte
Byte 398 or 445: CAS Latencies Supported, Second Byte
Byte 399 or 446: CAS Latencies Supported, Third Byte
Byte 400 or 447: CAS Latencies Supported, Fourth Byte..............................16
2.3.5 Byte 401 or 448: Minimum CAS Latency Time (tAAmin) ..............................17
2.3.6 Byte 402 or 449: Minimum RAS# to CAS# Delay Time (tRCDmin) ................ 18
2.3.7 Byte 403 or 450: Minimum Row Precharge Delay Time (tRPmin)...................19
2.3.8 Byte 404 or 451: Upper Nibbles for tRAS and tRC.......................................19
2.3.9 Byte 405 or 452: Minimum Active to Precharge Delay Time (tRASmin), Least
Significant Byte......................................................................................19
2.3.10 Byte 406 or 453: Minimum Active to Active/Refresh Delay Time (tRCmin), Least
Significant Byte......................................................................................20
2.3.11 Byte 407 or 454: Minimum Refresh Recovery Delay Time (tRFC1min), LSB .... 21
2.3.12 Byte 409 or 456: Minimum Refresh Recovery Delay Time (tRFC2min), LSB .... 21
2.3.13 Byte 411 or 458: Minimum Refresh Recovery Delay Time (tRFC4min), LSB .... 22
2.3.14 Byte 413 or 460: Upper Nibble for tFAW....................................................22
2.3.15 Byte 414 or 461: Minimum Four Activate Window Delay Time (tFAWmin), Least
Significant Byte......................................................................................23
2.3.16 Byte 415 or 462: Minimum Activate to Activate Delay Time (tRRD_Smin),
Different Bank Group..............................................................................23
2.3.17 Byte 416 or 463: Minimum Activate to Activate Delay Time (tRRD_Lmin), same
bank group............................................................................................24
2.3.18 Bytes 417-422 or 464-469: RSVD in Profiles..............................................24
2.3.19 Bytes 423 & 424 or 470 & 471: RSVD for Supplier Custom Mods .................. 25
2.3.20 Byte 425 or 472: Fine Offset for Minimum Row Active to Row Active Delay Time
(tRRD_Lmin), same bank group ...............................................................25
2.3.21 Byte 426 or 473: Fine Offset for Minimum Row Active to Row Active Delay Time
(tRRD_Smin), different bank group...........................................................25
2.3.22 Byte 427 or 474: Fine Offset for Minimum Active to Active/Refresh Delay Time
(tRCmin)...............................................................................................25
2.3.23 Byte 428 or 475: Fine Offset for Minimum Row Precharge Delay Time (tRPmin)..
25
2.3.24 Byte 429 or 476: Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
25
4 Intel Confidential IBL# 541356
Tables
2-1 tCKAVGmin SPD Calculations Using MTB and FTB..........................................................13
2-2 Timing Parameters using both MTB and FTB.................................................................13
2-3 Two’s Complement Encoding Fine Timebase Offset........................................................13
IBL# 541356 Intel Confidential 5
Revision History
§ §
Document
Number
Revision
Number
Description Revision Date
IBL# 541356 1.0 • Initial release December 2013
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