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Version 3.0
System Design Guide
Revision 0.3
August 15, 2008
MXM Version 3.0 System Design Guide
Document Change History
Revision Date Responsible Description of Change
0.1 May 9, 2008 TL, SM Draft Release
0.2 May 22, 2008 TL,SM,TS Updated Figures
Minor changes throughout
0.3 August 15, 2008 TL, SM Minor changes throughout
Added section 8 (system designer checklist)
ii
MXM Version 3.0 System Design Guide
Table of Contents
Reference Documents ....................................................................................................1
1 Introduction ................................................................................................................2
2 Power and Initialization..............................................................................................4
2.1. Power and Initialization Signals............................................................................... 4
2.2. Power Rail Requirements........................................................................................ 4
2.3. Power-Up Sequencing and Initialization ................................................................... 5
2.3.1. Power-Up Sequence...................................................................................... 5
2.3.2. Reset........................................................................................................... 6
2.3.3. Signal Management During Initialization ......................................................... 7
2.3.3.1. Isolating Key Module Outputs................................................................... 7
2.3.3.2. Module Voltage Application Restrictions..................................................... 8
2.4. Power-Down Sequencing........................................................................................ 8
2.5. Power Level Hardware Control ................................................................................ 9
2.6. Power Plane Layout Recommendations.................................................................. 10
2.7. Bulk Capacitors.................................................................................................... 11
3 PCI Express Interface................................................................................................12
3.1. PEX Signals ......................................................................................................... 12
3.2. PEX Layout and Routing Recommendations............................................................ 13
3.2.1. Reference Plane Guidelines ......................................................................... 14
3.2.2. Signal Breakout Area Guidelines................................................................... 14
3.2.3. AC Coupling Capacitors ............................................................................... 16
3.2.4. Layout and Routing Rules............................................................................ 19
3.2.5. Test Points and Probe Structures ................................................................. 21
3.2.6. MXM V 3.0 Connector ................................................................................. 21
4 Digital Display Interfaces..........................................................................................22
4.1. Dual Mode DisplayPort Signals .............................................................................. 22
4.2. Dual Mode DisplayPort Layout and Routing Recommendations................................. 23
4.2.1. DisplayPort Routing and Placement Guidelines .............................................. 24
4.2.2. AC Coupling Capacitors ............................................................................... 24
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MXM Version 3.0 System Design Guide
4.3. Hot Plug Detection............................................................................................... 24
4.4. DVI and HDMI Dongle Support ............................................................................. 25
4.5. Native DVI or HDMI Connector Support ................................................................. 26
4.5.1. DVI and HDMI Signal Mapping..................................................................... 28
4.5.2. High Definition Audio .................................................................................. 28
4.5.3. HDMI CEC.................................................................................................. 28
4.6. LVDS Signals ....................................................................................................... 29
4.7. LVDS Layout and Routing Recommendations ......................................................... 30
4.7.1. LVDS Signal Layout and Routing Guidelines .................................................. 30
4.7.2. LVDS DDC.................................................................................................. 31
4.8. Internal Panel Control Signals ............................................................................... 31
4.8.1. PNL_PWR_EN............................................................................................. 31
4.8.2. PNL_BL_EN................................................................................................ 31
4.8.3. PNL_BL_PWM............................................................................................. 31
5 Analog Display Interfaces .........................................................................................33
5.1. Analog Display Signals ......................................................................................... 33
5.2. VGA.................................................................................................................... 34
5.3. VGA Layout Recommendations ............................................................................. 34
5.3.1. RGB Filtering.............................................................................................. 37
5.3.2. VGA SYNCH Filtering................................................................................... 37
5.3.3. 5V Level Sync Signals for Legacy Monitors .................................................... 38
5.3.4. DDC .......................................................................................................... 39
5.4. TV-Out ............................................................................................................... 39
5.5. TV-Out Layout Recommendations ......................................................................... 40
5.6. VGA and TV Multiplexer Design............................................................................. 41
5.6.1. VGA and TV Multiplexer Layout Recommendations ........................................ 42
5.7. TV-Out configurations .......................................................................................... 43
5.7.1. Single Composite-Out ................................................................................. 43
5.7.2. Single S-Video............................................................................................ 44
5.7.3. Composite and S-Video with Separate Connectors ......................................... 45
5.7.4. Composite and S-Video with Shared Connectors............................................ 46
5.7.5. HDTV-Out Only .......................................................................................... 47
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MXM Version 3.0 System Design Guide
6 System Management.................................................................................................48
6.1. System Management Signals ................................................................................ 48
6.2. Primary Display Selection ..................................................................................... 49
6.3. General Purpose Interface .................................................................................... 49
6.4. Resume, Suspend, and Soft-Off Operations............................................................ 49
6.5. System Management Bus ..................................................................................... 49
6.6. Other Optional Features ....................................................................................... 50
6.6.1. Embedded ROM Interface ........................................................................... 50
6.6.2. Module Detection ....................................................................................... 50
6.6.3. OEM Customizations ................................................................................... 51
7 Thermal Management ...............................................................................................52
7.1. Thermal Management Signals ............................................................................... 52
7.1.1. Thermal Over-temperature Alert .................................................................. 52
7.1.2. Thermal Alert ............................................................................................. 53
7.1.3. Fan PWM ................................................................................................... 53
8 System Designer Checklist........................................................................................54
9 Appendix....................................................................................................................56
9.1. VIA placement Considerations............................................................................... 56
9.2. Use of Transition Vias .......................................................................................... 60
9.3. Use of Transition Capacitors ................................................................................. 61
9.4. Symmetrical Routing ............................................................................................ 62
9.5. Proper Via Placement........................................................................................... 63
9.6. Serpentining Guidelines........................................................................................ 64
9.7. DDC EMI Filter Requirements................................................................................ 65
9.8. DDC Level Shifting and Backdrive Prevention Circuits.............................................. 65
9.9. Docking Station Port ............................................................................................ 67
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