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首页24口全千兆交换机方案RTL8382L RTL8218B RTL8231L设计参考原理图
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1
1
A A
Serdes 0
Serdes 1
Serdes 2 Serdes 3 Serdes 4 Serdes 5
FHY [0..7] FHY [16..23]FHY [8..15]
RESET
MDC/MDIO
Strapping Pin
REG_IF_SEL
EEPROMTYPE
DIS_PHYAUTO_UP
LED_MODE1
LED_MODE0
EN_DECRYPT
MEM_TYPE1
MEM_TYPE0
SEL_XTAL_CLK
CLK_M_EE1
CLK_M_EE0
PWRBLINK1
PWRBLINK0
DIS_EEE
Note on board
Close to IC
LED CONNECTOR
FIBER X2
SPI FLASH&EEPROM
SLAVE SPI & EEPROM
SDS_PDOWN_EN
CPU_SLEEP
close to 82L
close to 82L
close to 82L
SPI_ADDR_SEL
NOTE:
RTL8382L Reserved Pin Must Be Floating
EEPROMTYPE
RSVD
GND
GND
GND
GND
VDDL
VDDL
VDDL
VDDL
VDDL
VDDH
VDDH
VDDH
VDDH
VDDIO
VDDIO
GND
VDDH
VDDH
GND
GND
VDDL VDDL
VDDL
GND
VDDIO
GND
GND GND
VDDH
GND
VDDH
GND GND
GND
VDDL
VDDL
VDDH
VDDH
VDDL
GND
GND
GND
VDDL
GND
VDDH
VDDL
GND
VDDL
GND
VDDH
GND
VDDL
8382L_CKOUT0 4
8382L_S0TXP 4
8382L_S0TXN 4
8382L_S0RXP 4
8382L_S0RXN 4
8382L_S1TXN 4
8382L_S1TXP 4
8382L_S1RXN 4
8382L_S1RXP 4
8382L_S3RXP 5
8382L_S3RXN 5
8382L_S3TXP 5
8382L_S3TXN 5
8382L_S2RXN 5
8382L_S2RXP 5
8382L_S2TXN 5
8382L_S2TXP 5
8382L_CKOUT2 5
MDIAP[15..8] 8
MDIAN[15..8] 8
MDIBP[15..8] 8
MDIBN[15..8] 8
MDICP[15..8] 8
MDICN[15..8] 8
MDIDP[15..8] 8
MDIDN[15..8] 8
8382L_RESETB 2
LED_DAT 6
LED_CLK 6
SPI_CLK 2
SPI_SO/SIO1 2
SPI_SI/SIO0 2
SPI_CS#0 2
UART0_TX/REG_IF_SEL 1,2,3
UART0_RX 2
EEPROMTYPE 1,3
SSPI_CLK/I2C_CLK 2
SSPI_SI/I2C_DAT 2
MDIO_P 4,5
MDC_P 4,5
XI 2
XO 2
UART0_TX/REG_IF_SEL 1,2,3
EEPROMTYPE 1,3
SSPI_SO/DIS_PHYAUTO_UP 3
LED_MODE1 3
LED_MODE0 3
EN_DECRYPT 3
MEM_TYPE1 3
MEM_TYPE0 3
SEL_XTAL_CLK 3
CLK_M_EE1 3
CLK_M_EE0 3
PWRBLINK1 3
PWRBLINK0 3
DIS_EEE 3
8382L_S5RXP
8382L_S5RXN
8382L_S5TXP
8382L_S5TXN
8382L_S4RXN
8382L_S4RXP
8382L_S4TXN
8382L_S4TXP
SDS_PDOWN_EN 3
CPU_SLEEP 3
SPI_ADDR_SEL 3
Title
Size Document Number Rev
Date: Sheet of
P03-RTL8382L
1.0C
1 10Friday, November 10, 2016
Realtek Semiconductor Corp.
Title
Size Document Number Rev
Date: Sheet of
P03-RTL8382L
1.0C
1 10
Title
Size Document Number Rev
Date: Sheet of
P03-RTL8382L
1.0
RTL8382L RTL8218B RTL8231 Re Design
C
1 10
C56
0.1uf
C0603
C58
0.1uf
C0603
C52
0.1uf
C0603
C54
0.1uf
C0603
C44
0.1uf
C0603
C47
100uF/10V
C3528
C17
1uf
c0603
C13
0.1uf
C0603
R10NI_33
R0603
R7 33R
R0603
R6 33R
T1
1X2PIN
C3
0.1uf
C0603
C200.1uf
C65
0.1uf
C0603
R1 33R
C59
0.1uf
C0603
C35
0.1uf
C0603
JS1
PAD
1
R8 510R
R0603
C40
0.1uf
C0603
R4 33R
C220.1uf
C66
0.1uf
C0603
C4
0.1uf
C0603
RTL8382L
U1
P2MDIBP
1
P2MDIBN
2
AVDDL
3
P2MDICP
4
P2MDICN
5
P2MDIDP
6
P2MDIDN
7
AVDDH
8
P3MDIAN
10
P3MDIBN
12
AVDDL
13
AVDDH
14
P3MDICN
16
P3MDIDP
17
P3MDIDN
18
AGND
20
MDIREF
21
AVDDL
22
RTT1
23
RTT2
24
DVDDL
26
DVDDH
27
RESERVED1
28
EEPROMTYPY
30
RESERVED3
31
RESERVED4
32
DVDDL
33
DVDDL
34
DVDDH
35
AVDDH
36
P4MDIAP
37
P4MDIAN
38
P4MDIBP
39
P4MDIBN
40
AVDDH
41
AVDDL
42
P4MDICP
43
P4MDIDP
45
P4MDIDN
46
AVDDH
47
P5MDIAP
48
P5MDIAN
49
P5MDIBP
50
P5MDIBN
51
AVDDL
52
P5MDICP
53
P5MDICN
54
VDDIO
163
RESERVED24
164
CPU_SLEEP
166
RESERVED26
167
RESERVED27
168
MEM_TYPE[1]
169
MEM_TYPE[0]
170
CLK_M_EE[1]
171
CLK_M_EE[0]
172
EN_DECRYPT
173
RESERVED28
174
RESERVED30
176
VDDIO
177
DVDDL
178
VX
179
CKOUT0
180
SVDDL
181
S0TXP
182
S0TXN
183
S0RXP
184
S0RXN
185
SVDDH
186
S1TXP
188
S1RXN
189
S1RXP
190
SVDDL
191
DVDDL
192
AVDDH
193
P0MDIAP
194
P0MDIAN
195
AVDDL
198
P0MDICP
199
P0MDICN
200
P0MDIDP
201
P0MDIDN
202
AVDDH
203
P1MDIAP
204
P1MDIAN
205
P1MDIBP
206
P1MDIBN
207
AVDDL
208
P1MDICP
209
P1MDICN
210
P1MDIDP
211
P1MDIDN
212
PLLVDDL
213
ATESTCK0
214
P2MDIAP
215
P2MDIAN
216
P5MDIDP
55
P5MDIDN
56
PLLVDDL
57
ATESTCK1
58
P6MDIAP
59
P6MDIAN
60
P6MDIBP
61
P6MDIBN
62
AVDDL
63
P6MDICP
64
P6MDICN
65
P6MDIDP
66
P6MDIDN
67
AVDDH
68
P7MDIAP
69
P7MDIAN
70
P7MDIBP
71
P7MDIBN
72
AVDDL
73
P7MDICP
74
P7MDICN
75
P7MDIDP
76
P7MDIDN
77
AVDDH
78
DVDDL
79
CKOUT2
80
SVDDL
81
S2TXP
82
S2TXN
83
S2RXN
85
SVDDL
86
S3TXN
87
S3TXP
88
S3RXN
89
S3RXP
90
SVDDH
91
CKOUT4
92
SVDDL
93
S4TXP
94
S4TXN
95
S4RXP
96
S4RXN
97
SVDDL
98
S5TXN
99
S5TXP
100
S5RXN
101
S5RXP
102
SVDDL
103
AVDDH_PLL
104
XO
105
XI
106
DVDDL
108
DVDDL
109
GPIO3
110
GPIO2
111
GPIO1
112
GPIO0
113
RESET#
114
DVDDH
115
SSPI_CS#
116
SSPI_SO/DIS_PHYAUTO_UP
117
SSPI_SI/I2C_DAT
118
SSPI_CLK/I2C_CLK
119
MDC
120
MDIO
121
LED_CLK
122
LED_DAT
123
UART0_TX/REG_IF_SEL
124
UART0_RX
125
DVDDL
126
SPI_CS#0
127
SPI_SI/SIO0
128
SPI_SO/SIO1
129
SPI_CLK
130
DVDDH
131
RESERVED5
133
RESERVED6
134
RESERVED7
135
RESERVED9
137
RESERVED10
138
DVDDL
139
RESERVED12
141
RESERVED13
142
RESERVED14
143
RESERVED16
145
RESERVED17
146
RESERVED18
147
RESERVED20
149
DIS_EEE
150
PWRBLINK[0]
151
PWRBLINK[1]
152
SEL_XTAL_CLK
153
SDS_PDOWN_EN
154
SPI_ADDR_SEL
155
LED_MODE[1]
156
LED_MODE[0]
157
RESERVED21
158
RESERVED22
159
DVDDL
160
RESERVED23
161
VDDIO
162
P3MDIAP
9
P3MDIBP
11
P3MDICP
15
AVDDH
19
AVDDH
25
RESERVED2
29
P4MDICN
44
S2RXP
84
AVDDL_PLL
107
VDDIO
132
RESERVED8
136
RESERVED11
140
RESERVED15
144
RESERVED19
148
RESERVED25
165
RESERVED29
175
S1TXN
187
P0MDIBP
196
P0MDIBN
197
GND
217
C61
10uF
c0805
C62
0.1uf
C0603
C32
0.1uf
C0603
C70
0.1uf
C0603
C31
100uF/10V
C3528
C60
0.1uf
C0603
C6
0.1uf
C0603
C9
5pF
C76
0.1uf
C0603
C240.1uf
C10
5pF
C0603
C45
0.1uf
C0603
C1
18pf
C0603
C75
4.7uf
c0603
C53
0.1uf
C0603
C8
5pF
C37
0.1uf
C0603
C15
4.7uf
c0603
C46
0.1uf
C0603
C71
0.1uf
C0603
C39
0.1uf
C0603
C69
0.1uf
C0603
C74
0.1uf
C0603
C67
0.1uf
C0603
C50
0.1uf
C0603
C42
0.1uf
C0603
C5
0.1uf
C0603
C55
4.7uf
c0603
C68
0.1uf
C0603
C63
0.1uf
C0603
T2
1X2PIN
C7
5pF
C28
1000pf
C0603
R11NI_33
R0603
C11
5pF
C0603
C34
0.1uf
C0603
C30
1000pf
C0603
R2 33R
C64
0.1uf
C0603
C12
4.7uf
c0603
C41
10uF
c0805
R5 33R
C36
0.1uf
C0603
C48
0.1uf
C0603
C51
0.1uf
C0603
C33
0.1uf
C0603
R12
2.49k_1%
R0603
C49
0.1uf
C0603
C210.1uf
L1
BLM18PG331SN1
L0603
1 2
C57
0.1uf
C0603
C27
1uf
c0603
R9 33R
R0603
C14
0.1uf
C0603
C18
0.1uf
C0603
C72
0.1uf
C0603
R3 33R
C29
1uf
c0603
C260.1uf
C38
0.1uf
C0603
C190.1uf
C16
0.1uf
C0603
C250.1uf
C73
0.1uf
C0603
C230.1uf
C2
1uf
c0603
C43
0.1uf
C0603
LED_MODE0
MEM_TYPE1
MEM_TYPE0
CLK_M_EE1
CLK_M_EE0
EN_DECRYPT
8382L_CKOUT0
S0TXP
S0TXN
8382L_S0RXP
8382L_S0RXN
S1TXN
S1TXP
8382L_S1RXN
8382L_S1RXP
MDIAP8
MDIAN8
MDIBP8
MDIBN8
MDICP8
MDICN8
MDIDP8
MDIDN8
MDIAP9
MDIAN9
MDIBP9
MDICP9
MDICN9
MDIBN9
MDIDP9
MDIDN9
MDIAP10
MDIAN10
MDIBP10
MDIBN10
MDICP10
MDICN10
MDIDP10
MDIDN10
MDIAP11
MDIAN11
MDIBP11
MDIBN11
MDICP11
MDICN11
MDIDP11
MDIDN11
MDIREF
MDIAP12
MDIAN12
MDIBP12
MDIBN12
MDICP12
MDICN12
MDIDP12
MDIDN12
MDIAP13
MDIAN13
MDIBP13
MDIBN13
MDICP13
MDICN13
MDIAP14
MDIAN14
MDIBN14
MDICP14
MDICN14
MDIDP14
MDIDN14
MDIAP15
MDIAN15
MDIBP15
MDIBN15
MDICP15
MDICN15
MDIDP15
MDIDN15
S2TXP
S2TXN
8382L_S2RXP
8382L_S2RXN
S3TXN
S3TXP
8382L_S3RXN
8382L_S3RXP
8382L_S4RXP
8382L_S4RXN
8382L_S5TXN
8382L_S5TXP
8382L_S5RXN
8382L_S5RXP
XO
XI
LED_MODE1
SEL_XTAL_CLK
PWRBLINK1
PWRBLINK0
DIS_EEE
EEPROMTYPE
UART0_RX
UART0_TX/REG_IF_SEL
LED_DAT_82L
LED_CLK_82L
MDIO
MDC
SSPI_CLK/I2C_CLK
SSPI_SI/I2C_DAT
SSPI_SO/DIS_PHYAUTO_UP
SSPI_CS#
8382L_RESETB
8382L_S0TXP
8382L_S0TXN
8382L_S1TXN
8382L_S1TXP
8382L_S2TXP
8382L_S2TXN
8382L_S3TXP
8382L_S3TXN
8382L_S4TXP
8382L_S4TXN
8382L_RESETB
MDC_P
8382L_S4RXP
8382L_S4RXN
8382L_S5TXN
8382L_S5TXP
8382L_S5RXN
8382L_S5RXP
8382L_S4TXP
8382L_S4TXN
SPI_CLK
SPI_SO/SIO1
SPI_SI/SIO0
SPI_CS#0
UART0_RX
UART0_TX/REG_IF_SEL
LED_DAT
LED_CLK
SSPI_CLK/I2C_CLK
SSPI_SI/I2C_DAT
MDIDN13
MDIDP13
MDIBP14
8382L_CKOUT2
SDS_PDOWN_EN
CPU_SLEEP
MDIO_P
MDIO
MDC
LED_CLK_82L
LED_DAT_82L
LED_CLK
LED_DAT
SPI_ADDR_SEL
SPI_CS#0
SPI_SI/SIO0
SPI_SO/SIO1
SPI_CLK
AVDDL_PLL
AVDDL_PLL
1
1
A A
8382L_RESETB
TEXT
RESET
OFF-PAGE
OFF-PAGE
SPI FLASH &EEPROM
SLAVE SPI & EEPROM
OFF-PAGE
OFF-PAGE
Layout Note:
place close to RTL8382L
OFF-PAGE
RSVD
CLOCK
GND
GND
GND
GND
GND
GND
GND
GND
VDDH
VDDH
VDDH
VDDH
VDDH
GND
VDDH
GND
8382L_RESETB 1
PHY_RESETB 4,5,6
SPI_CS#0 1
SPI_SI/SIO0 1
SPI_CLK 1
SPI_SO/SIO1 1
SSPI_CLK/I2C_CLK 1
SSPI_SI/I2C_DAT 1
XI 1
XO 1
UART0_RX 1
UART0_TX/REG_IF_SEL 1,3
Title
Size Document Number Rev
Date: Sheet of
MISC
1.0C
2 10Thursday, November 09, 2016
Realtek Semiconductor Corp.
Title
Size Document Number Rev
Date: Sheet of
MISC
1.0C
2 10
Realtek Semiconductor Corp.
Title
Size Document Number Rev
Date: Sheet of
MISC
1.0C
2 10
Realtek Semiconductor Corp.
R16
10K
R13
10K
J2
NI_HEADER_1X4(2.54mm)
1
2
3
R24 1.5k
C77
0.1uf
R23 1.5k
R15
10K
Y1
25MHz
XTAL_49S
1 2
U2
SPI_FLASH
CS
1
SO
2
WP
3
VSS
4
VCC
8
HOLD
7
SCLK
6
SI
5
C80 27pF
C0603
R25 1.5k
C81 0.1uf
U3
24C02
DIP_8
A0
1
A1
2
A2
3
GND
4
SDA
5
SCLK
6
WP
7
VCC
8
D1
1N4148
MLL34
1 2
C78
10uF
C0805
R21
NI_1K
B1
TL3301G
A
1
B
2
R22
NI_1M
R0603
C79 27pF
C0603
R14
2.2K
R0603 R17 0R
R0603
R19
NI_1K
R18 0R
R0603
J1
NI_HEADER_1X4(2.54mm)
1
2
3
4
R20 NI_0
R0603
XI
XO
SPI_CS#0
SPI_SI/SIO0
SPI_WP# SPI_CLK
SPI_SO/SIO1
SPI_CS#0
SPI_SI/SIO0
SPI_CLK
SPI_SO/SIO1
SSPI_CLK/I2C_CLK
SSPI_SI/I2C_DAT
8382L_RESETB
PHY_RESETB
SSPI_SI/I2C_DAT
SSPI_CLK/I2C_CLK
UART0_TX/REG_IF_SEL
UART0_RX
RTL8382L RTL8218B RTL8231 Re Design
1
1
A A
OFF-PAGE
PIN STRAPPING
Disable Asic auto power up PHY
:
0b0: enable asic auto power up phy;
0b1: disable asic auto power up phy.
Enable serdes power down mode:
0b0: disable sds4 and sds5 power down mode
,
serdes will work at cfg mode.
0b1: enable sds4 and sds5 power down mode.
DIS_PHYAUTO_UP
REG_IF_SEL
Select switch core register access interface:
0b0: I2C;
0b1: SPI slave.
EEPROMTYPE
Select EEPROM Address Byte Size:
0b0: 1-byte;
0b1: 2-byte.
SDS_PDOWN_EN
LED_MODE[1:0]
Select LED mode:
0b00: serial LED mode;
0b01: Scan Single mode;
0b10: Scan Bicolor mode;
0b11: disable LED.
CPU_SLEEP
CPU_SLEEP
0b0: CPU is always under reset state;
0b1: CPU is in normal state.
SPI_ADDR_SEL
Select address mode for SPI flash:
0b0: 3Bytes address;
0b1: 4Bytes address.
EN_DECRYPT
Enable or disable decrypt for flash.
0b0: disable decrypt;
0b1: enable decrypt.
MEM_TYPE[1:0]
Select Memory Type for SOC.
0b00: Select SPI flash
0b01: Reserved
0b10: Select SPI flash
0b11: Select EEPROM
SEL_XTAL_CLK
Selection XTAL input is 25M or 125M
0b0: 25M;
0b1:125M.
CLK_M_EE[1:0]
When MEM_TYPE Select is SPI Flash:
This Strapping Pin Selects the Initial Clock for
The Memory Controller.
0b00: Reserved for test;
0b01: Reserved for test;
0b10: 100MHz;
0b11: Reserved for test.
When MEM_TYPE Select is EEPROM:
CLK_M_EE[0] is used to select SOC EEPROM
address byte size.
0b0: 1-byte address0b1: 2-byte address
PWRBLINK[1:0]
Select LED power on Blinking timer:
0b00: Disable;
0b01: 800ms;
0b10: 1.6s;
0b11: 3.2s.
DIS_EEE
Disable 1000M EEE and 100M EEE function:
0b0: enable EEE function;
0b1: disable EEE function;
GND
VDDH
VDDIO
VDDHVDDIO
GND
VDDIO
CLK_M_EE1 1
MEM_TYPE1 1
CLK_M_EE0 1
LED_MODE1 1
MEM_TYPE0 1
PWRBLINK1 1
LED_MODE0 1
PWRBLINK0 1
EEPROMTYPE 1
UART0_TX/REG_IF_SEL 1,2
EN_DECRYPT 1
SSPI_SO/DIS_PHYAUTO_UP 1
SEL_XTAL_CLK 1
DIS_EEE 1
SDS_PDOWN_EN 1
CPU_SLEEP 1
SPI_ADDR_SEL 1
Title
Size Document Number Rev
Date: Sheet of
PIN_STRAPPING 1.0B
3 10Thursday, November 09, 2016
Realtek Semiconductor Corp.
Title
Size Document Number Rev
Date: Sheet of
PIN_STRAPPING 1.0B
3 10
Realtek Semiconductor Corp.
Title
Size Document Number Rev
Date: Sheet of
PIN_STRAPPING 1.0B
3 10
Realtek Semiconductor Corp.
R36 47K
R51 47K
R27 4.7k
R42 47K
R40 47K
R47 47K R48 NI_47K
R26
100R_1%
R30 4.7k R31 NI_4.7k
R34 47K
R35 47K
R38 47K
R53 NI_47K
R56 NI_47K
R49 47K
R37 NI_47K
R39 NI_47K
R44 NI_47K
R55 47K
R29 4.7k
D2
NI_1N4001
MLL41
12
R45 47K
R41 NI_47K
R52 NI_47K
R50 NI_47K
R32
100R_1%
R28 NI_4.7k
R54 47K
R43 47K
R33 47K
R46 NI_47K
PWRBLINK0
DIS_EEE
UART0_TX/REG_IF_SEL
EEPROMTYPE
SSPI_SO/DIS_PHYAUTO_UP
LED_MODE1
LED_MODE0
EN_DECRYPT
MEM_TYPE1
MEM_TYPE0
SEL_XTAL_CLK
CLK_M_EE1
CLK_M_EE0
PWRBLINK1
SDS_PDOWN_EN
CPU_SLEEP
SPI_ADDR_SEL
RTL8382L RTL8218B RTL8231 Re Design
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