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SGMII Specification 1.8
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The Serial Gigabit Media Independent Interface (SGMII) is designed to satisfy the following requirements
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Document Number ENG-46158
Revision Revision 1.8
Author Yi-Chin Chu
Project Manager JR Rivers
Serial-GMII Specification
The Serial Gigabit Media Independent Interface (SGMII) is designed to satisfy the following
requirements:
• Convey network data and port speed between a 10/100/1000 PHY and a MAC with
significantly less signal pins than required for GMII.
• Operate in both half and full duplex and at all port speeds.
Change History
D ef initions
MII – Media Independent Interface: A digital interface that provides a 4-bit wide datapath
between a 10/100 Mbit/s PHY and a MAC sublayer. Since MII is a subset of GMII, in this
document, we will use the term “GMII” to cover all of the specification regarding the MII
interface.
Revision Date Description
1.8 April 27, 2005 Add shim to the PHY transmit datapath to suppress TX_ER when TX_EN
is not asserted
1.7 July 20, 20001 Clarify data sampling and also the possible loss of the first byte of pream-
ble.
1.6 Jan 4, 20001 Added specifications for Cisco Systems Intellectual Property.
1.5 Aug 4, 2000 Specified the data pattern for the beginning of the frame (preamble, SFD)
for the frames sent from the PHY to make the PCS layer work properly.
1.4 June 30, 2000 Took out Jabber info, changed tx_Config_Reg[0] from 0 to 1 to make Auto-
Negotiation work
1.3 April 17, 2000 Increased allowable input and output common mode range. The output high
and low voltages were also increased appropriately. Added specification for
output over/undershoot. Added note about AC coupling and clock recovery.
1.2 Feb 8, 2000 Added timing budget analysis and reduced LVDS input threshold to +/- 50
mV.
1.1 Nov 10, 1999 Incoporated Auto-Negotiation Process for update of link status
1.0 Oct. 14, 1999 Initial Release
S e r i a l - G M I I S p e c i fi c a t i on : E N G - 4 6 15 8 R e v i s i on 1. 8
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GMII – Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide
datapath between a 1000 Mbit/s PHY and a MAC sublayer. It also supports the 4-bit wide MII
interface as defined in the IEEE 802.3z specification. In this document, the term “GMII”
covers all 10/100/1000 Mbit/s interface operations.
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Ov erv iew
SGMII uses two data signals and two clock signals to convey frame data and link rate
information between a 10/100/1000 PHY and an Ethernet MAC. The data signals operate at
1.25 Gbaud and the clocks operate at 625 MHz (a DDR interface). Due to the speed of
operation, each of these signals is realized as a differential pair thus providing signal integrity
while minimizing system noise.
Figure 1 illustrates the simple connections in a system utilizing SGMII.
The transmit and receive data paths leverage the 1000BASE-SX PCS defined in the IEEE
802.3z specification (clause 36). The traditional GMII data signals (TXD/RXD), data valid
signals (TX_EN/RX_DV), and error signals (TX_ER/RX_ER) are encoded, serialized and
output with the appropriate DDR clocking. Thus it is a 1.25 Gbaud interface with a 625 MHz
clock. Carrier Sense (CRS) is derived/inferred from RX_DV, and collision (COL) is logically
derived in the MAC when RX_DV and TX_EN are simultaneously asserted. There is a small
block in the PHY transmit path to suppress TX_ER in full duplex mode when TX_EN is not
asserted.
Control information, as specified in Table 1, is transferred from the PHY to the MAC to signal
the change of the control information. This is achieved by using the Auto-Negotiation
functionality defined in Clause 37 of the IEEE Specification 802.3z. Instead of the ability
advertisement, the PHY sends the control information via its tx_config_Reg[15:0] as specified
in Table 1 whenever the control information changes. Upon receiving control information, the
MAC acknowledges the update of the control information by asserting bit 14 of its
tx_config_reg{15:0] as specified in Table 1.
SGMII details source synchronous clocking; however, specific implementations may desire to
recover clock from the data rather than use the supplied clock. This operation is allowed;
however, all sources of data must generate the appropriate clock regardless of how they clock
receive data.
RX
RXCLK
TX
TXCLK
PHYM A C
CRS
COL
RX_CK
RX_DV
RX_ER
RXD[7:0]
GTX_CLK
TX_CLK
TX_EN
TX_ER
8
8
TXD[7:0]
802.3z
Transmit
PCS
802.3z
Receive
PCS
802.3z
Synch
COL
RX_CLK
RX_DV
RX_ER
RXD[7:0]
GTX_CLK
TX_CLK
TX_EN
TX_ER
TXD[7:0]
CRS
8
802.3z
Synch
802.3z
Transmit
PCS
8
802.3z
Receive
PCS
F i g u r e 1 S G M I I C on n e c t i v i t y
802.3z Auto-Negotiation
802.3z Auto-Negotiation
*
* TX_ER Suppression
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