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CoreSight Technology System Design Guide
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ARM® Compiler armlink User Guide provides user information for the ARM linker, armlink. It describes the basic linker functionality, image structure, BPABI and SysV support, GNU ld script support, how to access image symbols, and how to use scatter files.
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Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved.
ARM DGI 0012D (ID062610)
CoreSight
™
Technology
System Design Guide
ARM DGI 0012D Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved. ii
ID062610 Non-Confidential
CoreSight Technology
System Design Guide
Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved.
Release Information
The table below shows the release state and change history of this document.
Proprietary Notice
Words and logos marked with
®
or
™
are registered trademarks or trademarks of ARM
®
in the EU and other countries,
except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or
damage arising from the use of any information in this document, or any error or omission in such information, or any
incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Confidentiality Issue Change
29 September 2004 Non-Confidential A First release
20 July 2007 Non-Confidential B Updated for r1p0
29 April 2010 Non-Confidential C Updated for STM and TMC
25 June 2010 Non-Confidential D Update on Clock domain interactions
ARM DGI 0012D Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved. iii
ID062610 Non-Confidential
Contents
CoreSight Technology System Design Guide
Preface
About this guide .......................................................................................................... ix
Feedback .................................................................................................................. xiii
Chapter 1 Introduction
1.1 About CoreSight systems ........................................................................................ 1-2
1.2 CoreSight features ................................................................................................... 1-4
Chapter 2 CoreSight Components and Systems
2.1 About CoreSight systems and components ............................................................. 2-2
2.2 CoreSight components ............................................................................................ 2-4
2.3 CoreSight system examples .................................................................................. 2-13
2.4 Illegal structures ..................................................................................................... 2-16
Chapter 3 Features of CoreSight Technology and ETM Architectures
3.1 About CoreSight Technology and ETM architectures features ................................ 3-2
3.2 CoreSight component data ...................................................................................... 3-3
3.3 Architectural features of ARM trace sources ......................................................... 3-15
Chapter 4 Debug Access
4.1 About debug access ................................................................................................ 4-2
4.2 Access to the system ............................................................................................... 4-3
4.3 Access to debug components ................................................................................. 4-5
4.4 Mixed legacy and DAP debug ................................................................................. 4-9
4.5 Debug activity across the chip ............................................................................... 4-11
4.6 Typical trigger signals ............................................................................................ 4-14
Contents
ARM DGI 0012D Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved. iv
ID062610 Non-Confidential
Chapter 5 Trace Capture
5.1 About trace capture ................................................................................................. 5-2
5.2 Designing your trace system ................................................................................... 5-4
5.3 Using your system ................................................................................................. 5-11
Chapter 6 Implementation
6.1 About implementation ............................................................................................. 6-2
6.2 Power control ........................................................................................................... 6-3
6.3 Power domains and system design ........................................................................ 6-5
6.4 Power control enabled components ....................................................................... 6-7
6.5 Debug and system power up ................................................................................. 6-11
6.6 Clock domains ....................................................................................................... 6-13
6.7 Resets .................................................................................................................... 6-15
6.8 Tools controlled debug reset ................................................................................. 6-19
6.9 Interface timing ...................................................................................................... 6-20
6.10 Timing, synthesis, and placement ......................................................................... 6-22
Appendix A Revisions
Glossary
ARM DGI 0012D Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved. v
ID062610 Non-Confidential
List of Tables
CoreSight Technology System Design Guide
Change history ................................................................................................................................ ii
Table 3-1 DAP component features for Debug Ports .................................................................................. 3-4
Table 3-2 DAP component features for Access Ports ................................................................................. 3-4
Table 3-3 Trace source component features .............................................................................................. 3-6
Table 3-4 Trace source HTM and ITM features .......................................................................................... 3-7
Table 3-5 Link component features, part 1 ................................................................................................. 3-8
Table 3-6 Link component features, part 2 ................................................................................................. 3-9
Table 3-7 Sink component features, part 1 ............................................................................................... 3-10
Table 3-8 Sink component features, part 2 ............................................................................................... 3-11
Table 3-9 Debug component features, part 1 ........................................................................................... 3-13
Table 3-10 Debug component features, part 2 ........................................................................................... 3-14
Table 3-11 ARM trace source component features, part 1 ......................................................................... 3-15
Table 3-12 ARM trace source component features, part 2 ......................................................................... 3-16
Table 4-1 CPU connections ...................................................................................................................... 4-14
Table 4-2 ETM connections ...................................................................................................................... 4-14
Table 4-3 HTM, ITM, and STM connections ............................................................................................. 4-15
Table 4-4 TPIU, ETB, and TMC connections ............................................................................................ 4-15
Table 5-1 Effect of different tracing levels on ETM bandwidth requirements .............................................. 5-7
Table 6-1 Power-up request and acknowledge signal connections .......................................................... 6-12
Table 6-2 CSDK clocks ............................................................................................................................. 6-13
Table 6-3 CSDK reset signals ................................................................................................................... 6-15
Table 6-4 ATB master interface parameters, input to register, register to output ..................................... 6-20
Table 6-5 ATB slave interface parameters, input to register, register to output ........................................ 6-21
Table A-1 Differences between issue B and issue C ...............................................................................
... A-1
Table A-2 Differences between issue C and issue D .................................................................................. A-2
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