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A
pplication Note
BCM5
38X/BCM5396
5
38X_5396-AN105-R
5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 January 20, 2010
BC
M5396 and BCM5389/BCM5387
Design Guidelines
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the
trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or
the EU. Any other trademarks or trade names mentioned are the property of their respective owners.
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2010 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
REVISION HISTORY
Revision Date Change Description
538X_5396-AN105-R 01/20/10 Updated:
• “GMII Interface” on page 28
• “Supply Voltages” on page 50
• “Input Voltage and Noise Tolerance” on page 52
• “Design Considerations for Main Power Supply” on page 53
• “Specific Power Supply Decoupling Recommendations for the
BCM5389 and BCM5387” on page 55
- “PLLAVDD, PLLAVDD2” on page 55
- “SAVDD” on page 55
- “DVDD” on page 55
- “PLLDVDD” on page 56
- “OVDD” on page 56
- “OVDD2” on page 56
- “XTALVDD” on page 56
Added:
• Table 14: “BCM5389/BCM5387 Power Supply Requirements,” on
page 50
• Table 15: “BCM5396 Power Supply Requirements,” on page 50
• Table 16: “BCM5389/BCM5387 Power Voltage and Noise
Tolerance,” on page 52
• Table 17: “BCM5396 Power Voltage and Noise Tolerance,” on
page 53
• “Ferrite Bead” on page 55
• “Specific Power Supply Decoupling Recommendations for the
BCM5396” on page 56
538X_5396-AN104-R 11/11/09 Updated:
• Figure 28: “EEPROM First Entry Encoding,” on page 45
538X_5396-AN103-R 02/12/07 Updated:
• Table 12: “Designing with Unused Pins,” on page 29
Revision History
BROADCOM
January 20, 2010 • 538X_5396-AN105-R Page 3
®
BCM538X/BCM5396 Application Note
538X_5396-AN102-R 04/24/06 Updated:
• Table 7: “GMII Signal Descriptions,” on page 19
• “Transmit GMII” on page 19
• Figure 12: “GMII Interface,” on page 20
• Figure 13: “RGMII Signals,” on page 21
• Table 8: “RGMII Signal Descriptions,” on page 22
•“RGMII Transmit” on page 23
• Figure 14: “Original Transmit RGMII Timing,” on page 23
• Figure 15: “Delayed (RGMII-ID) Transmit RGMII Timing,” on page
24
• Figure 29: “EEPROM Interface Connection,” on page 38
• Table 14: “Power Supply Requirements,” on page 42
538X_5396-AN101-R 06/08/05 Minor corrections
538X_5396-AN100-R 05/18/05 Initial release
Revision Date Change Description
Table of Contents BCM538X/BCM5396 Application Note
BROADCOM
January 20, 2010 • 538X_5396-AN105-R Page 4
®
Table of Contents
Section 1: Overview ........................................................................................................ 11
Eight-Port Stand-Alone Switch.....................................................................................................................12
System Interfaces...................................................................................................................................12
Sample Applications...............................................................................................................................12
Section 2: Selected Design Recommendations................................................................. 14
PCB Stackup ..................................................................................................................................................14
Component Placement.................................................................................................................................14
Decoupling/Bypassing..................................................................................................................................14
Magnetics .....................................................................................................................................................14
Routing..........................................................................................................................................................15
L0 Plane Stitching with Vias .........................................................................................................................15
Section 3: MAC and Media Interfaces.............................................................................. 16
SGMII Interface.............................................................................................................................................16
Configuring SGMII Mode........................................................................................................................17
Pin Descriptions .....................................................................................................................................17
SGMII Receive ........................................................................................................................................17
SGMII Transmit ......................................................................................................................................17
Auto-negotiation and Control Information Exchanged Between Links .................................................18
SGMII Layout..........................................................................................................................................18
SerDes Interface ...........................................................................................................................................18
Configuring SerDes Mode ......................................................................................................................19
Pin Descriptions .....................................................................................................................................19
SerDes Receive.......................................................................................................................................20
SerDes Transmit.....................................................................................................................................20
Auto-negotiation and Control Information Exchanged Between Links .................................................20
Connecting SerDes to Fiber Module ......................................................................................................22
SerDes to Backplane/Cable Interface ....................................................................................................23
SerDes/SGMII Layout Guidelines .................................................................................................................23
RvMII Interface.............................................................................................................................................25
3.3V MII I/Os ..........................................................................................................................................25
Pin Descriptions .....................................................................................................................................25
Transmit RvMII.......................................................................................................................................26
Receive RvMII ........................................................................................................................................26
RvMII Driver Compliance .......................................................................................................................26
Table of Contents BCM538X/BCM5396 Application Note
BROADCOM
January 20, 2010 • 538X_5396-AN105-R Page 5
®
RvMII Layout ..........................................................................................................................................26
GMII Interface...............................................................................................................................................28
3.3V GMII I/Os........................................................................................................................................28
Pin Descriptions .....................................................................................................................................28
Transmit GMII ........................................................................................................................................28
Receive GMII..........................................................................................................................................29
GMII Driver Compliance.........................................................................................................................29
GMII Layout............................................................................................................................................29
RGMII Interface ............................................................................................................................................30
Signal Descriptions.................................................................................................................................31
Pin Descriptions .....................................................................................................................................31
RGMII Transmit ......................................................................................................................................32
RGMII Receive........................................................................................................................................32
RGMII Delayed Timing ...........................................................................................................................33
Delayed Transmit Timing ................................................................................................................33
Delayed Receive Timing..................................................................................................................33
Data and Control Signal Encoding..........................................................................................................34
RGMII Layout .........................................................................................................................................35
Section 4: I/O Pins........................................................................................................... 36
1.2V/2.5V with 3.3V Tolerance ....................................................................................................................36
Internal Pull-Ups and Pull-Downs ................................................................................................................36
Configuring the Programming Interfaces ....................................................................................................36
Reset .............................................................................................................................................................37
Unused Pins ..................................................................................................................................................38
Section 5: Programming Interfaces.................................................................................. 39
SPI Compatible Programming Interface ......................................................................................................39
External PHY Registers ...........................................................................................................................40
Clock Polarity and Phase........................................................................................................................40
Read and Write Examples......................................................................................................................41
Normal Mode Read ........................................................................................................................41
Fast Mode Read ..............................................................................................................................43
Normal Mode Write .......................................................................................................................44
EEPROM Interface Connection.....................................................................................................................45
MDC/MDIO Interface ...................................................................................................................................46
Master: External PHY Registers .............................................................................................................47
Internal SerDes Transceiver and Pseudo PHY ........................................................................................48
剩余67页未读,继续阅读
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