没有合适的资源?快使用搜索试试~ 我知道了~
首页Getting Started with UVM
Getting Started with UVM
需积分: 15 22 下载量 87 浏览量
更新于2023-03-16
评论 2
收藏 4.51MB PDF 举报
There are a multitude of books out there to help you hone your Verification skills, as almost every Digital IC professional will tell you. The available books run the gamut of quality and ease of use. The major strength of this book is a place where many of those books fall down – they are not what they claim to be. Vanessa’s book is a great example of exactly what it claims to be – a guide for the “beginner”. “Beginner” is used loosely in this context because the book does not shy away from advanced concepts (the Factory, register package prediction, etc.)
资源详情
资源评论
资源推荐
Project Manager: JL Gray
Designer: Vanessa R. Cooper
Editor: Georgellen Burnett
Verilab Publishing is an imprint of Verilab, Inc.
8310 North Capital of Texas Highway
Suite 215
Austin, TX 78731, USA
© 2013, 2012 Verilab, Inc. – http://www.verilab.com
All rights reserved. No part of this book may be reproduced, in
any form or by any means, without permission in writing from
the publisher.
ISBN-13: 978-0615819976 (Verilab Publishing)
ISBN-10: 0615819974
eBook ISBN: 978-1-63003-105-3
About Verilab, Inc.
Verilab specializes in verification environment development,
methodology definition, and project planning for chip design
projects. Since our founding in 2000, we have worked on over
200 projects across more than 50 companies. With offices in the
US, UK, Germany, and Canada, our goal is to facilitate
consistent, successful results for our clients.
SystemVerilog + UVM/OVM/VMM
Verilab is involved with the IEEE-1800 (SystemVerilog)
committee and, as an Accellera member, an active participant in
the VIP-TSC (UVM). Our consultants have access to up-to-date
technical information on the latest methodologies and trends.
Specman/e + eRM/UVMe
Looking for a seasoned Specmaniac to join your project team?
Many of our consultants have years of experience bulding
verification environments in e.
Verification Leadership
Verilab has helped companies big and small in both direct
leadership and consulting roles to help navigate the minefield
between design concept and tapeout.
Clock Domain Crossing Design and Verification
Verilab has helped companies around the world do a better job
understanding CDC design and verification best practices.
SystemRDL, UVM-ML
Verilab engineers are keeping an eye on emerging Accellera
standards in the areas of register modeling and multi-language
verification methodologies.
How We Work With Clients
Onsite
Our engineers can work directly with your project team onsite
at your office.
Remote/Onsite
When our engineers are located remotely from your facility, we
recommend they come onsite for 1-2 weeks for a project kickoff.
Typically, they would come onsite for one week per month for
the duration of the project.
Consulting
Sometimes you have the right team in place but need some
additional knowledge and guidance to get the job done. A
Verilab consultant can come onsite for 1-2 weeks for an
intensive ramp up on topics such as verification planning,
SystemVerilog/UVM testbench development, or CDC design and
verification. We would then follow up with you over the next
several months either via short phone calls or occasional
onsite visits to check on progress.
Leadership Coaching
Have you recently moved into a verification leadership
position? Work with a senior member of Verilab’s engineering
剩余108页未读,继续阅读
bulabala
- 粉丝: 0
- 资源: 6
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- RTL8188FU-Linux-v5.7.4.2-36687.20200602.tar(20765).gz
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
- SPC统计过程控制程序.pptx
- SPC统计方法基础知识.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论0